公开(公告)号：US5250817A

公开(公告)日：1993-10-05

申请号：US928984

申请日：1992-08-12

Applicant: Richard L. Fink

Inventor： Richard L. Fink

IPC: H01L39/22 ,  B05D5/12 ,  H01B12/00

CPC classification number: H01L39/225 ,  Y10S505/702

Abstract: A superconducting Josephson junction, circuit and method of manufacture is provided for maintaining optimal chemical and structural compositions at the interface region between an insulating barrier (12) and a pair of superconductor electrodes (14) and (16). Each superconductor electrode of the Josephson junction comprises a chemical selected from the group consisting of Ba1-xKxBiO3 and Ba1-xRbxBiO3. In addition, the insulating barrier (12), formed between the electrode pair (14) and (16), is made of a chemical compound including an alkali element. The alkali element within the barrier region serves to eliminate or reduce ion migration from the BKBO or BRBO superconducting electrodes. The alkali element in the barrier (12) as well as the superconductor electrodes (14) and (16) also provides good structural matching at the barrier-electrode interface regions. As a result of the chemical and structural matching between the superconductor electrodes and the barrier, an SIS Josephson tunnel junction and integrated circuit is formed having high quality histeretic properties.

Abstract translation: 提供超导约瑟夫逊结，电路和制造方法，用于在绝缘屏障（12）和一对超导体电极（14）和（16）之间的界面区域保持最佳化学和结构组成。 约瑟夫逊结的每个超导体电极包含选自Ba1-xKxBiO3和Ba1-xRbxBiO3的化学物质。 此外，形成在电极对（14）和（16）之间的绝缘屏障（12）由包含碱元素的化合物制成。 阻挡区域内的碱元素用于消除或减少从BKBO或BRBO超导电极的离子迁移。 势垒（12）中的碱元素以及超导体电极（14）和（16）也在阻挡 - 电极界面区域提供了良好的结构匹配。 由于超导体电极和屏障之间的化学和结构匹配的结果，形成了具有高质量组成特性的SIS约瑟夫逊隧道结和集成电路。

公开(公告)号：US5240671A

公开(公告)日：1993-08-31

申请号：US891029

申请日：1992-06-01

Applicant: David H. Carey

Inventor： David H. Carey

IPC: B28B7/00 ,  B28B7/16 ,  B28B7/18 ,  C04B35/622 ,  C04B41/45 ,  C04B41/81 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12

CPC classification number: C04B41/009 ,  B28B7/0064 ,  B28B7/16 ,  B28B7/18 ,  C04B35/622 ,  C04B41/4578 ,  C04B41/81 ,  H01L21/486 ,  H05K3/0014 ,  C04B2111/00844 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09118 ,  H05K2203/1476 ,  H05K3/107 ,  H05K3/1258 ,  Y10T29/49163

Abstract: A method of forming recessed patterns in insulators is described. One embodiment of the invention is directed to ceramic green sheet fabrication by providing a sculptured plastic tape mold which includes a floor, a plurality of sidewalls adjacent to and extending above the floor and a plurality of protrusions on and extending above the floor, casting a ceramic slurry into the mold such that the slurry contacts the floor, the sidewalls and the protrusions, and drying the slurry so as to produce a ceramic green sheet with a recessed pattern that replicates the shapes of the protrusions. The ceramic green sheet may be removed from the mold and filled with a conductor before firing; alternatively, the ceramic green sheet can be fired before removing the mold to form a rigid ceramic substrate which is then filled with a conductor.

Abstract translation: 描述了在绝缘体中形成凹陷图案的方法。 本发明的一个实施方案涉及通过提供一种雕刻的塑料带模具来提供陶瓷生片，所述模具包括地板，与地板相邻并在地板上方延伸的多个侧壁，以及在地板上方并在其上延伸的多个突起，铸造陶瓷 浆料进入模具，使得浆料接触地板，侧壁和突起，并干燥浆料，以便产生具有复制突起形状的凹陷图案的陶瓷生片。 陶瓷生片可以从模具中取出并在烧成之前用导体填充; 或者，可以在去除模具之前烧制陶瓷生片以形成刚性陶瓷衬底，然后填充导体。

公开(公告)号：US5227013A

公开(公告)日：1993-07-13

申请号：US735572

申请日：1991-07-25

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01L21/48 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K3/0035 ,  H01L21/486 ,  H05K1/0393 ,  H05K2201/0166 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1338 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/4076 ,  Y10T29/49155

Abstract: A method for forming via holes in a multilayer structure in a single step. The invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to the portions of the first metal lines. Thereafter conductive metal can be deposited in the via holes. The method is particularly well suited for fabricating copper/polymer substrates.

Abstract translation: 一种在一个步骤中在多层结构中形成通孔的方法。 本发明包括在基底上设置包括在第一电介质下方的第一金属线的第一层，在第一层上设置第二层，第二层包括第二电介质下面的第二金属线，使得每个第一金属线的一部分不在任何第二金属之下 并且形成通过第二电介质延伸到第二金属线并且通过第二电介质和第一电介质延伸到第一金属线的部分的通孔。 此后，导电金属可以沉积在通孔中。 该方法特别适用于制造铜/聚合物基材。

公开(公告)号：US5210936A

公开(公告)日：1993-05-18

申请号：US817214

申请日：1992-01-06

Applicant: Richard L. Simmons ,  James D. Wehrly, Jr. ,  Michael J. Bertram

Inventor： Richard L. Simmons ,  James D. Wehrly, Jr. ,  Michael J. Bertram

IPC: H01L21/00 ,  H01L23/495

CPC classification number: H01L24/50 ,  H01L21/67144 ,  H01L23/49558 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49121 ,  Y10T29/5149 ,  Y10T29/515

Abstract: The excise and lead form of TAB leads bonded to an integrated circuit chip. Leads extending beyond a sidewall are clamped between a first clamp and a form anvil at a first portion spaced from the chip. The leads are also clamped between an excise/form tool and a second clamp at a second portion spaced further from the chip than the first portion. An excise blade cuts the leads outside the second portion. Then the excise/form tool, second clamp and excise blade move downwards in a curved path toward the chip to form a first lead corner against the form anvil and a second lead corner against the excise/form tool without splaying or galling the leads.

Abstract translation: TAB引脚的切割和引线形式引线结合到集成电路芯片。 延伸超过侧壁的引线在与芯片间隔开的第一部分处夹在第一夹具和砧座之间。 在比第一部分更远离芯片的第二部分处，引线也夹在消费/成型工具和第二夹具之间。 切割刀将第二部分之外的引线切割。 然后，切割/成形工具，第二夹具和切割刀片以弯曲的路径向下移动朝向芯片，以形成抵抗砧座的第一引导角和抵靠消费/形成工具的第二引导角，而不会使引线绷直或磨损。

公开(公告)号：US5167992A

公开(公告)日：1992-12-01

申请号：US667778

申请日：1991-03-11

Applicant: Charles W. C. Lin ,  Ian Y. K. Yee

Inventor： Charles W. C. Lin ,  Ian Y. K. Yee

IPC: C23C18/16 ,  H05K3/24

CPC classification number: H05K3/244 ,  C23C18/1608 ,  C23C18/1635 ,  C23C18/1889 ,  C23C18/2006 ,  C23C18/208 ,  C23C18/32 ,  C23C18/42 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2203/0392 ,  H05K2203/095

Abstract: A method for electrolessly plating an overcoat metal on a metal conductor disposed on a dielectric surface of a substrate. The method includes removing carbonized film from the dielectric surface by applying a plasma discharge, acid treating the metal conductor by dipping the substrate in a first acid solution in order to clean the surface of the metal conductor, activating the metal conductor to allow electroless plating thereon by dipping the substrate in a metal activator solution, deactivating the dielectric surface to prevent electroless plating thereon without deactivating the metal conductor by dipping the substrate in a second acid solution, and plating an overcoat metal on the metal conductor by dipping the substrate in an electroless plating solution so that the overcoat metal plates on and coats the metal conductor without plating on the dielectric surface.

Abstract translation: 在设置在基板的电介质表面上的金属导体上无电镀电镀金属的方法。 该方法包括通过施加等离子体放电来从电介质表面去除碳化膜，通过将基底浸渍在第一酸溶液中来酸化处理金属导体，以清洁金属导体的表面，激活金属导体以允许金属导体在其上进行无电镀 通过将基底浸渍在金属活化剂溶液中，使电介质表面失活以防止其上化学镀，而不使金属导体通过将基底浸渍在第二酸溶液中而使金属导体失活，并且通过将基底浸渍在无电镀中而在金属导体上镀覆外涂层金属 电镀溶液，使得外涂金属板在金属导体上涂覆并涂覆在电介质表面上。

公开(公告)号：US5137597A

公开(公告)日：1992-08-11

申请号：US683897

申请日：1991-04-11

Applicant: John W. Curry, II ,  Ian Y. K. Yee

Inventor： John W. Curry, II ,  Ian Y. K. Yee

IPC: H01L21/768 ,  H01L23/522 ,  H05K3/46

CPC classification number: H01L21/76885 ,  H01L23/5226 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/09701

Abstract: A method for fabricating metal pillars in an electronic component. The method includes providing a base with spaced vias in a top surface, depositing an electrically conductive metal into the vias and over the top surface of the base so that a metal layer with an uneven top surface forms over the base, and planarizing the metal by polishing. The polishing can remove the entire metal layer leaving metal pillars in and aligned with the base. Or the polishing can be completed before removing the metal layer and metal above the base between the vias can be etched to form metal pillars with uniform heights which extend above the base. The invention is well suited for fabricating high-density multilayer copper/polyimide electrical interconnects.

Abstract translation: 一种用于在电子部件中制造金属柱的方法。 该方法包括在顶表面中提供具有间隔通孔的基底，将导电金属沉积到通孔中并在基底的顶表面上方，使得具有不平坦顶表面的金属层形成在基底上，并且通过 抛光。 抛光可以去除整个金属层，留下金属柱并与基座对齐。 或者可以在去除金属层和基底之上的金属之前完成抛光，可以蚀刻通孔，以形成均匀高度的金属柱，该高度在基底之上延伸。 本发明非常适用于制造高密度多层铜/聚酰亚胺电互连。

公开(公告)号：US5124175A

公开(公告)日：1992-06-23

申请号：US614340

申请日：1990-11-15

Applicant: Robert F. Miracky ,  Tom J. Hirsch ,  Colin A. MacKay

Inventor： Robert F. Miracky ,  Tom J. Hirsch ,  Colin A. MacKay

IPC: H05K1/00 ,  H05K3/10 ,  H05K3/14 ,  H05K3/22 ,  H05K3/34

CPC classification number: H05K3/225 ,  H05K1/0293 ,  H05K2201/0305 ,  H05K2203/043 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1338 ,  H05K2203/173 ,  H05K3/105 ,  H05K3/146 ,  H05K3/34

Abstract: Solder reflow on an electrical interconnect substrate between a plurality of electrical contacts. The method includes coating the contacts with tin/lead solder, depositing a wetting metal between the contacts, and heating the substrate to at least the melting point of the solder so that the solder melts, reflows across the wetting metal and connects or links the contacts. The entire surface of a customizable copper/polyimide substrate can be personalized by solder links and TAB leads from surface-mounted integrated circuits can simultaneously be soldered to the substrate.

Abstract translation: 在多个电触点之间的电互连基板上的焊料回流。 该方法包括用锡/铅焊料涂覆触点，在触点之间沉积润湿金属，并将衬底加热至至少焊点的熔点，使得焊料熔化，在整个润湿金属上回流并连接或连接触点 。 可定制的铜/聚酰亚胺基板的整个表面可以通过焊接链接个性化，并且来自表面安装的集成电路的TAB引线可以同时焊接到基板。

公开(公告)号：US5120572A

公开(公告)日：1992-06-09

申请号：US605806

申请日：1990-10-30

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H05K1/16 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0317 ,  H05K2201/09563 ,  H05K2203/0315 ,  H05K2203/1142 ,  H05K3/061 ,  H05K3/4647 ,  Y10S148/014 ,  Y10S148/136

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be connected selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for cooper/polyimide substrates.

Abstract translation: 一种用于制造用于多芯片模块的高密度互连基板中的集成电阻器的方法。 此外，电阻材料可以选择性地连接到绝缘体中，以可选地允许在相对较少的步骤中同时制造集成电阻器和电容器。 该工艺非常适用于铜/聚酰亚胺基板。

公开(公告)号：US5113483A

公开(公告)日：1992-05-12

申请号：US538833

申请日：1990-06-15

Applicant: James D. Keeler ,  Eric J. Hartman

Inventor： James D. Keeler ,  Eric J. Hartman

IPC: G06N3/04

CPC classification number: G06K9/4628 ,  G06N3/04

Abstract: A neural network includes an input layer comprising a plurality of input units (24) interconnected to a hidden layer with a plurality of hidden units (26) disposed therein through an interconnection matrix (28). Each of the hidden units (26) is a single output that is connected to output units (32) in an output layer through an interconnection matrix (30). Each of the interconnections between one of the hidden units (26) to one of the output units (32) has a weight associated therewith. Each of the hidden units (26) has an activation in the i'th dimension and extending across all the other dimensions in a non-localized manner in accordance with the following equation: ##EQU1## that the network learns by the Back Propagation method to vary the output weights and the parameters of the activation function .mu..sub.hi and .sigma..sub.hi.

Abstract translation: 神经网络包括输入层，其包括互连到隐藏层的多个输入单元（24），其中通过互连矩阵（28）设置有多个隐藏单元（26）。 每个隐藏单元（26）是通过互连矩阵（30）连接到输出层中的输出单元（32）的单个输出。 隐藏单元（26）中的一个与输出单元（32）中的一个的每个互连具有与之相关联的权重。 隐藏单元（26）中的每一个都具有第i维的激活，并且以非本地化的方式延伸到所有其他维度中：根据下面的等式：网络通过反向传播方法学习 改变激活函数mu hi和sigma hi的输出权重和参数。

公开(公告)号：US5091339A

公开(公告)日：1992-02-25

申请号：US557427

申请日：1990-07-23

Applicant: David H. Carey

Inventor： David H. Carey

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H05K3/00 ,  H05K3/10 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/485 ,  H05K3/0032 ,  H05K3/0041 ,  H05K3/005 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/0166 ,  H05K2201/09563 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1189 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4661 ,  Y10S438/94 ,  Y10S438/945

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

Abstract translation: 可以在相对较少的步骤中以低成本的蚀刻和图案化技术形成通过部分延伸的通孔和完全延伸穿过例如基板或集成电路的电互连中的绝缘层的通孔。 然后可以以相对较少的步骤在通道和通孔中填充电导体。 在一个实施例中，将通孔和通道暴露的不可侵蚀的硬掩模放置在聚酰亚胺层上，暴露通孔但覆盖通道的可侵蚀的软掩模置于硬掩模上，并施加等离子体蚀刻。 蚀刻通孔区域直到软掩模完全侵蚀，然后蚀刻通孔区和通道区，以提供部分蚀刻的通道和完全蚀刻的通孔。 此后，种子层沉积在互连上，并且导电层电解沉积在种子层上，基本上填充通道和通孔。 然后通过抛光将互连表面平坦化，直到电导体仅保留在通道和通孔中。