公开(公告)号：US20180257930A1

公开(公告)日：2018-09-13

申请号：US15975349

申请日：2018-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Simon Joshua Jacobs

IPC: B81C1/00 ,  G02B26/08 ,  B81B3/00 ,  G02B1/115 ,  B81B7/00

CPC classification number: B81C1/00317 ,  B81B3/0083 ,  B81B7/0067 ,  B81B2201/042 ,  B81B2207/015 ,  B81C1/00047 ,  B81C1/00119 ,  B81C1/00261 ,  B81C1/00269 ,  B81C1/00595 ,  B81C2201/014 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771 ,  G02B1/115 ,  G02B26/0833

Abstract: An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.

公开(公告)号：US09919917B2

公开(公告)日：2018-03-20

申请号：US14514356

申请日：2014-10-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jong Woon Kim ,  Won Kyu Jeung

IPC: B81C1/00 ,  G01P15/08 ,  G01P15/09 ,  G01P15/18 ,  G01C19/56 ,  B81B3/00 ,  C09K13/08 ,  C09K13/00

CPC classification number: B81C1/00158 ,  B81B3/0062 ,  B81B3/007 ,  B81B2201/0235 ,  B81B2203/053 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/01 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C09K13/00 ,  C09K13/08 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/0922 ,  G01P15/18 ,  G01P2015/084 ,  G01P2015/0871

Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.

公开(公告)号：US20170267516A1

公开(公告)日：2017-09-21

申请号：US15615238

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B2203/0163 ,  B81B2207/012 ,  B81C1/00801 ,  B81C1/00952 ,  B81C2201/013 ,  B81C2201/014 ,  B81C2203/0792

Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

公开(公告)号：US09676606B2

公开(公告)日：2017-06-13

申请号：US14699070

申请日：2015-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou

IPC: H01L21/768 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B2203/0163 ,  B81B2207/012 ,  B81C1/00801 ,  B81C1/00952 ,  B81C2201/013 ,  B81C2201/014 ,  B81C2203/0792

Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

公开(公告)号：US20160376147A1

公开(公告)日：2016-12-29

申请号：US15171002

申请日：2016-06-02

Applicant: Nivarox-FAR S.A.

Inventor： Alex Gandelhman ,  Andre Pin

IPC: B81C1/00 ,  G04D99/00

CPC classification number: B81C1/00619 ,  B81B2201/035 ,  B81B2203/0384 ,  B81C1/00103 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0138 ,  B81C2201/014 ,  B81C2201/0188 ,  B81C2201/0198 ,  G04B13/02 ,  G04B13/026 ,  G04B13/027 ,  G04D99/00

Abstract: The invention relates to a silicon-based component with at least one reduced contact surface which, formed from a method combining at least one oblique side wall etching step with a “Bosch” etch of vertical side walls, improves, in particular, the tribology of components formed by micromachining a silicon-based wafer.

Abstract translation: 本发明涉及具有至少一个还原接触表面的硅基组分，其由至少一个倾斜侧壁蚀刻步骤与垂直侧壁的“博世”蚀刻法组合的方法形成，特别是改进了摩擦学 通过微加工硅基晶片形成的部件。

公开(公告)号：US09490137B2

公开(公告)日：2016-11-08

申请号：US14616004

申请日：2015-02-06

Applicant: Robert Bosch GmbH

Inventor： Simon Armbruster ,  Frank Fischer ,  Johannes Baader ,  Rainer Straub

IPC: H01L21/311 ,  H01L21/02 ,  B81C1/00

CPC classification number: H01L21/311 ,  B81C1/00801 ,  B81C2201/014 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228

Abstract: A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step.

Abstract translation: 用于从两个半导体层构成诸如微机械部件的分层结构的绝缘和/或蚀刻停止层的方法包括在第一半导体层的第一侧上形成第一蚀刻掩模，执行 第一蚀刻步骤，从第一外侧开始，用于构造第一半导体层，在第二半导体层的第二侧上形成第二蚀刻掩模，并且执行第二蚀刻步骤，从第二外侧开始，用于 构造第二半导体层。 在执行第一蚀刻步骤之后并且在进行第二蚀刻步骤之前，至少一个蚀刻保护材料沉积在至少一个第一沟槽的至少一个沟槽壁上，该第一沟槽在第一蚀刻步骤中被蚀刻。

公开(公告)号：US09481572B2

公开(公告)日：2016-11-01

申请号：US14574937

申请日：2014-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Simon Joshua Jacobs

IPC: B81C1/00 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  B81B3/00

CPC classification number: B81C1/00317 ,  B81B3/0083 ,  B81B7/0067 ,  B81B2201/042 ,  B81B2207/015 ,  B81C1/00047 ,  B81C1/00119 ,  B81C1/00261 ,  B81C1/00269 ,  B81C1/00595 ,  B81C2201/014 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771 ,  G02B1/115 ,  G02B26/0833

Abstract: An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are etched into the bonded interposer/window wafer pair using the anti-reflective coating of the window wafer as an etch stop. After formation of the cavities, the bonded interposer/window wafer pair is bonded peripherally of die areas to the MEMS device wafer, with die area micromechanical elements sealed within respectively corresponding ones of the cavities.

Abstract translation: 一种光学电子器件和方法，其在将插入器晶片接合到窗口晶片之后通过插入器晶片形成空腔。 使用窗口晶片的抗反射涂层作为蚀刻停止层，将空腔蚀刻到粘合的插入物/窗玻璃对中。 在形成空腔之后，结合的插入物/窗口晶片对在管芯区域周围被结合到MEMS器件晶片，其中管芯区域微机械元件分别密封在相应的一个空腔中。

公开(公告)号：US09450109B2

公开(公告)日：2016-09-20

申请号：US13829106

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng ,  Te-Hao Lee ,  Chung-Hsien Lin

IPC: H01L29/84 ,  H01L21/02 ,  H01L21/50 ,  H01L21/30 ,  H01L21/20 ,  H01L23/00 ,  B81C1/00

CPC classification number: B81B7/0064 ,  B81B2203/04 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00238 ,  B81C2201/014 ,  B81C2203/0792 ,  H01L24/18 ,  H01L29/84 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/00

Abstract: A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate.

Abstract translation: 一种用于制造MEMS器件的方法包括提供在第一侧上具有牺牲层的微电机械系统（MEMS）衬底，提供包括多个空腔的载体，将MEMS衬底的第一侧接合在载体上， 在所述MEMS衬底的第二侧上形成第一接合材料层，向所述MEMS衬底施加牺牲层去除工艺，提供包括第二接合材料层并将所述半导体衬底接合在所述MEMS衬底的第二侧上的半导体衬底。

公开(公告)号：US20160244885A1

公开(公告)日：2016-08-25

申请号：US15033015

申请日：2013-10-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Roger A. McKay ,  Patrick W. Sadik

IPC: C23F1/16

CPC classification number: B81C1/00539 ,  B81B2201/058 ,  B81C1/00119 ,  B81C2201/0115 ,  B81C2201/014 ,  C23C14/5873 ,  C23F1/02 ,  C23F1/16 ,  H01M4/0492 ,  H01M4/386

Abstract: Etching islands are formed on a first face of a substrate and a second face of the substrate non-parallel to the first face. The first face and the second face of the substrate are concurrently exposed to a solution that reacts with the etching islands to concurrently form porous regions extending into the first face and the second face.

Abstract translation: 在基板的第一面和不平行于第一面的基板的第二面上形成蚀刻岛。 衬底的第一面和第二面同时暴露于与蚀刻岛反应的溶液，以同时形成延伸到第一面和第二面的多孔区域。

公开(公告)号：US20160137494A1

公开(公告)日：2016-05-19

申请号：US14943315

申请日：2015-11-17

Applicant: Seiko Epson Corporation

Inventor： Nobuyuki Tanaka

IPC: B81C1/00

CPC classification number: B81C1/00801 ,  B81C1/00158 ,  B81C1/00293 ,  B81C2201/014 ,  B81C2203/0136 ,  G01L5/06 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0054 ,  G01L9/0073 ,  G01L9/008 ,  H01L21/76264 ,  H01L21/76283

Abstract: An physical quantity sensor includes a substrate, a piezoelectric resistive element that is disposed on one surface side of the substrate, a wall portion that is disposed on the one surface side of the substrate so as to surround the piezoelectric resistive element in a plan view of the substrate, and a ceiling portion that is disposed on an opposite side to the substrate with respect to the wall portion and forms a cavity along with the wall portion, in which the wall portion includes an insulating layer, and wiring layers that surround the insulating layer together and have higher resistance to an etchant which can etch the insulating layer than resistance of the insulating layer.

Abstract translation: 物理量传感器包括基板，设置在基板的一个表面侧的压电电阻元件，设置在基板的一个表面侧上以围绕压电电阻元件的平面图的壁部分 基板和顶壁部分，其相对于壁部分设置在与基板相对的一侧上，并与壁部分一起形成空腔，壁部分包括绝缘层，以及围绕绝缘层的布线层 并且对蚀刻绝缘层的蚀刻剂具有比绝缘层的电阻更高的耐性。