公开(公告)号：US5208066A

公开(公告)日：1993-05-04

申请号：US877391

申请日：1992-04-30

申请人： Koji Fujisaki ,  Shunichi Numata ,  Takao Miwa ,  Takayoshi Ikeda ,  Hisae Shimanoki

发明人： Koji Fujisaki ,  Shunichi Numata ,  Takao Miwa ,  Takayoshi Ikeda ,  Hisae Shimanoki

IPC分类号： G03F7/00 ,  G11B5/31 ,  H01L21/312 ,  H01L21/3213 ,  H01L23/498 ,  H01L23/556 ,  H05K3/28 ,  H05K3/46

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G11B5/3163 ,  H01L21/312 ,  H01L21/32139 ,  H01L23/49894 ,  H01L23/556 ,  H01L2224/48463 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/28 ,  H05K3/4644 ,  Y10S438/953

摘要： A process of forming a patterned polyimide film includes the step of conversion of a polyimide precursor into polyimide. The improvement is imidizing the precursor by means of a chemical imidizing reagent. Typically a film of polyimide precursor is formed on a substrate, and mask which is negative with respect to the desired pattern is formed on the film. The film is contacted through the mask with a chemical imidizing reagent to effect imidization of unmasked portions, thereby forming polyimide. The mask and masked portions of the film are removed, leaving the desired polyimide pattern. High temperatures and harmful etchants can be avoided.

摘要翻译： 形成图案化聚酰亚胺膜的工艺包括将聚酰亚胺前体转化成聚酰亚胺的步骤。 改进之处在于通过化学酰亚胺化试剂将前体酰亚胺化。 通常，在基板上形成聚酰亚胺前体膜，在膜上形成相对于所需图案为负的掩模。 通过掩模将膜与化学酰亚胺化试剂接触以实现未掩蔽部分的酰亚胺化，由此形成聚酰亚胺。 除去膜的掩模和掩蔽部分，留下所需的聚酰亚胺图案。 可以避免高温和有害的蚀刻剂。

公开(公告)号：US5116775A

公开(公告)日：1992-05-26

申请号：US396686

申请日：1989-08-22

申请人： Hisao Katto ,  Jun Sugiura

发明人： Hisao Katto ,  Jun Sugiura

IPC分类号： H01L27/08 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76218 ,  H01L21/74 ,  H01L27/10805 ,  H01L27/105 ,  Y10S438/953

摘要： A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to .alpha.-rays and therefore free from soft errors caused by .alpha.-rays. Also disclosed is a method of producing said semiconductor memory device.

摘要翻译： 在形成场绝缘膜之后，同时形成设置在存储单元区域中的存储单元下方的重掺杂半导体区域和沟道截止区域，从而防止沟道阻挡区域渗入沟道区域， 从而获得耐受α射线的半导体存储器件，因此没有由α射线引起的软错误。 还公开了一种制造所述半导体存储器件的方法。

公开(公告)号：US5053848A

公开(公告)日：1991-10-01

申请号：US285440

申请日：1988-12-16

申请人： Theodore W. Houston ,  Ping Yang

发明人： Theodore W. Houston ,  Ping Yang

IPC分类号： G11C11/412 ,  H01L27/11 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  G11C11/4125 ,  H01L27/1104 ,  H01L29/78 ,  H01L29/7839 ,  Y10S257/904 ,  Y10S257/921 ,  Y10S438/953

摘要： A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).

摘要翻译： 公开了一种用于防止MOS电路中的单事件扰乱（SEU）的方法。 电阻区域（88,89）位于半导体器件中，使得当高能粒子通过器件和电阻区域（88,89）时，由粒子引起的杂散载流子将通过电阻区域（88,89） 89）导致电压降，这将防止MOS电路的镦粗。 为器件中的正常工作电流提供低电阻通路，使得器件的正常工作参数不受电阻区域（88,89）提供的保护的影响。

公开(公告)号：US5006479A

公开(公告)日：1991-04-09

申请号：US485687

申请日：1990-02-27

申请人： Jerry V. Brandewie

发明人： Jerry V. Brandewie

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  Y10S148/131 ,  Y10S148/15 ,  Y10S438/953

摘要： The radiation hardened NFET and process of the subject Methods and Structures for Improving Radiation Tolerance of Silicon Gate CMOS/Silicon on Sapphire Devices utilizes boron edge doping of a silicon epi island on sapphire at the island opposed edges in the region which will be the P-doped region of the finished transistor. Multiple boron ion implants are made into the silicon adjacent to the active region and driven-in to provide a uniform edge doping. Alternatively, a furnace containing a source of boron vapor and the sapphire wafer is used to dope the island edges at high temperatures.

摘要翻译： 辐射硬化的NFET和本发明的方法用于改善蓝宝石器件上的硅栅CMOS /硅的辐射容限的方法和结构利用在该区域的岛对置边缘处的蓝宝石上的硅外延岛的硼边缘掺杂， 最终晶体管的掺杂区域。 多个硼离子植入物被制成与有源区相邻的硅并被驱入以提供均匀的边缘掺杂。 或者，使用含有硼蒸汽源的炉和蓝宝石晶片来在高温下掺杂岛状边缘。

公开(公告)号：US4937756A

公开(公告)日：1990-06-26

申请号：US300582

申请日：1989-01-23

申请人： Je-Jung Hsu ,  Hsing-Hai Chen

发明人： Je-Jung Hsu ,  Hsing-Hai Chen

IPC分类号： H01L21/765

CPC分类号： H01L21/765 ,  Y10S257/906 ,  Y10S438/953

摘要： The invention relates to a radiation-hardened (R-H) bulk CMOS process which is compatible with DRAM production and a specific gated isolation structure (GIS). The GIS structure consists of a novel oxide-silicon nitride-oxynitride gate insulator and a LPCVD polysilicon gate. A simple but automatically generating process for creating GIS directly from an original non-R-H device is also described. This generating process is fast and can revise any commercial products to a R-H version. The GIS is always shunted to Vss potential of the circuit chip to assure R-H capability. The grounded GIS structure replaces conventional LOCOS field oxide, which suffers from large threshold voltage shift when exposed to irradiation. Radiation resistance of this gated isolation structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuits (.ltoreq.2um design rule).

摘要翻译： 本发明涉及与DRAM生产和特定的门控隔离结构（GIS）兼容的辐射硬化（R-H）体CMOS工艺。 GIS结构由新型氧化物 - 氮化硅 - 氮氧化物栅极绝缘体和LPCVD多晶硅栅极组成。 还描述了一种用于从原始非R-H设备直接创建GIS的简单但自动生成的过程。 这个生成过程很快，可以将任何商业产品修改为R-H版本。 GIS总是分流到电路芯片的Vss电位，以确保R-H能力。 接地的GIS结构代替常规的LOCOS场氧化物，当暴露于照射时，其具有大的阈值电压偏移。 该门控隔离结构（GIS）的抗辐射性适用于放射免疫VLSI集成电路（

公开(公告)号：US4936928A

公开(公告)日：1990-06-26

申请号：US336547

申请日：1989-04-10

申请人： Gerard J. Shaw ,  Jok Y. Go

发明人： Gerard J. Shaw ,  Jok Y. Go

IPC分类号： H01L21/761 ,  H01L27/02 ,  H01L27/082 ,  H01L29/10

CPC分类号： H01L21/761 ,  H01L27/0237 ,  H01L27/0821 ,  H01L29/10 ,  Y10S148/011 ,  Y10S438/953

摘要： A semiconductor structure is provided comprising a bulk substrate of semiconductor material having a first-type doping conductivity in a first dopant concentration. A first layer of semiconductor material is epitaxially formed on the substrate, such first layer having the first-type doping conductivity in a second dopant concentration lower than the first concentration. A second layer of semiconductor material is epitaxially formed on the first layer, the second layer having a second-type doping conductivity opposite to the first-type doping conductvity and thereby forming a P-N junction with the first layer. A plurality of regions, comprising semiconductor material having the first-type doping conductivity and extending through the second layer and a predetermined distance into the first layer, are further included for providing electrical isolation between active devices formed in different regions of the second layer. The thickness of the first layer is selected to be greater than the diffusion lengths of electron-hole pairs emitted by the bulk substrate in response to incident radiation and smaller than the thickness of the bulk substrate. With such arrangement, electron-hole pairs emitted by the substrate are substantially prevented from reaching such P-N junction, and few electron-hole pairs are emitted by the first layer, due to the small thickness thereof. Thus, electron-hole current at such P-N junction is reduced, thereby decreasing the effects of incident radiation on active devices formed in the semiconductor structure.

摘要翻译： 提供一种半导体结构，其包括具有第一掺杂浓度的第一类型掺杂导电性的半导体材料的块状衬底。 在衬底上外延形成第一层半导体材料，该第一层具有第一掺杂浓度低于第一浓度的第二掺杂浓度。 在第一层上外延形成第二层半导体材料，第二层具有与第一类掺杂电导相反的第二类掺杂导电性，从而与第一层形成P-N结。 还包括多个区域，其包括具有第一类型掺杂导电性并延伸穿过第二层并且预定距离进入第一层的半导体材料，用于在形成于第二层的不同区域中的有源器件之间提供电隔离。 第一层的厚度被选择为大于响应于入射辐射并且小于本体衬底的厚度的散装衬底发射的电子 - 空穴对的扩散长度。 通过这样的布置，基本上防止了由基板发射的电子 - 空穴对达到这种P-N结，并且由于其小的厚度，几乎没有电子 - 空穴对被第一层发射。 因此，在这种P-N结处的电子空穴电流减小，从而减少入射辐射对形成在半导体结构中的有源器件的影响。

公开(公告)号：US4775641A

公开(公告)日：1988-10-04

申请号：US911423

申请日：1986-09-25

申请人： Michael T. Duffy ,  Glenn W. Cullen

发明人： Michael T. Duffy ,  Glenn W. Cullen

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L21/336 ,  H01L21/86 ,  H01L29/32 ,  H01L29/786 ,  H01L21/423

CPC分类号： H01L29/78609 ,  H01L21/3226 ,  H01L21/86 ,  H01L29/32 ,  H01L29/78657 ,  Y10S257/906 ,  Y10S438/953

摘要： A radiation hardened silicon-on-insulator semiconductor device and method of making the same is disclosed. A region is formed in the silicon layer adjacent the insulating substrate which has a high density of naturally occurring crystallographic defects. This region substantially reduces the back-channel leakage that occurs when the device is operated after being irradiated.

摘要翻译： 公开了一种辐射硬化硅绝缘体上半导体器件及其制造方法。 在与绝缘基板相邻的硅层中形成具有高密度的天然存在的晶体缺陷的区域。 该区域基本上减少了在照射装置之后操作时发生的反向通道泄漏。

公开(公告)号：US4735917A

公开(公告)日：1988-04-05

申请号：US856280

申请日：1986-04-28

申请人： Doris W. Flatley ,  Kenneth M. Schlesier

发明人： Doris W. Flatley ,  Kenneth M. Schlesier

IPC分类号： H01L21/3105 ,  H01L21/86 ,  H01L21/473

CPC分类号： H01L21/31051 ,  H01L21/86 ,  Y10S438/953

摘要： A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands. Preferably, etching is continued for a time sufficient to completely expose the sidewall surfaces of the islaThe government has rights to this invention pursant to Subcontract No. A5ZV-522881-E-507 under Contract No. F04704-84-C-0061 awarded by the Department of the Air Force.

摘要翻译： 一种用于形成蓝宝石上硅集成电路的工艺包括在其主表面上具有至少一个硅岛的蓝宝石衬底上形成诸如二氧化硅的共形绝缘材料层; 在所述电介质层上形成平坦化材料层，各向异性地蚀刻所述平坦化材料足以暴露所述岛上的所述电介质层的表面的时间; 蚀刻电介质层足以暴露至少岛的顶表面的时间; 去除剩余的平坦化材料，在岛的暴露表面上生长薄层的栅极氧化物，并在其上提供导电多晶硅的图案化层。 电介质层的蚀刻可以继续至少部分地暴露岛的侧壁表面。 优选地，蚀刻持续一段时间，足以完全暴露岛的侧壁表面和与其相邻的表面的一部分。 在每个岛上形成单独的MOSFET，并且包括由沟道区域隔开的源极和漏极区域以及在沟道区域上的沟道电介质。

公开(公告)号：US4634473A

公开(公告)日：1987-01-06

申请号：US773772

申请日：1985-09-09

申请人： George A. Swartz ,  Carl W. Benyon, Jr.

发明人： George A. Swartz ,  Carl W. Benyon, Jr.

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/3115 ,  H01L29/49 ,  H01L29/51 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/4908 ,  H01L29/51 ,  H01L21/28211 ,  Y10S148/082 ,  Y10S148/083 ,  Y10S257/906 ,  Y10S438/953

摘要： A method for making a partially radiation hardened oxide adjacent an edge comprises forming an oxide layer on another layer with a temperature between about 975.degree. C. and 1400.degree. C., preferably between about 1000.degree. C. and 1200.degree. C. Then the structure of the oxide layer is damaged, such as by ion implantation, preferably with an inert element. Thereafter the oxide layer is annealed at a temperature between about 850.degree. C. and 900.degree. C., preferably at about 875.degree. C.

摘要翻译： 在边缘附近制造部分辐射硬化的氧化物的方法包括在温度在约975℃至1400℃之间，优选在约1000℃至1200℃之间的另一层上形成氧化物层。然后结构 的氧化物层被损坏，例如通过离子注入，优选用惰性元素。 此后，氧化物层在约850℃至900℃，优选约875℃的温度下退火。

公开(公告)号：US4318750A

公开(公告)日：1982-03-09

申请号：US107966

申请日：1979-12-28

申请人： Prosenjit Rai-Choudhury ,  John Bartko

发明人： Prosenjit Rai-Choudhury ,  John Bartko

IPC分类号： H01L21/263 ,  H01L7/54 ,  H01L21/22

CPC分类号： H01L21/263 ,  Y10S257/906 ,  Y10S438/953

摘要： A method for eliminating the latch-up effect in integrated circuits having parasitic pnpn structures has been described comprising the step of irradiating the circuit with high energy particulate ions to provide low lifetime regions in the circuit to lower parasitic transistor gain.The invention overcomes the problem of latch-up effect in integrated circuits where parasitic pnpn structures act as thyristors or silicon-controlled rectifiers which provide a low impedance path across the pnpn structure when the thyristor or silicon-controlled rectifier is turned on such as by transient ionizing radiation or by transient circuit voltages which forward bias the external junctions of the pnpn structure.

摘要翻译： 已经描述了一种用于消除具有寄生pnpn结构的集成电路中的闩锁效应的方法，其包括用高能微粒离子照射电路以在电路中提供低寿命区域以降低寄生晶体管增益的步骤。 本发明克服了在集成电路中的闩锁效应的问题，其中寄生pnpn结构用作晶闸管或硅控整流器，当晶闸管或可控硅整流器接通时，例如通过瞬态 电离辐射或通过正向偏置pnpn结构的外部结的瞬态电路电压。