公开(公告)号：US5950145A

公开(公告)日：1999-09-07

申请号：US814965

申请日：1997-03-11

申请人： Frankie F. Roohparvar

发明人： Frankie F. Roohparvar

IPC分类号： G01R31/317 ,  G11C29/46 ,  G01R31/28

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A test mode circuit for use in a data system includes a test mode code latch for receiving a test mode code. A switch, which when turned on, couples the test mode code latch to the input so that the test mode code can be transferred from the input to the test mode code latch. A test mode command decoder is coupled to the test mode code latch for decoding the test mode code to initiate a test mode of operation in the data system. A data storage unit is coupled to the test mode command decoder for storing a data bit which corresponds to a low voltage test mode enable signal. The data bit may be modified during the test mode of operation. A low voltage test mode circuit is coupled to the data storage unit which, after first being enabled by the low voltage test mode enable signal, can be controlled to turn the switch on and off. An enable signal generation circuit couples the low voltage test mode circuit to the switch for turning the switch on and off. A method of loading a test mode code into a data system is also disclosed.

公开(公告)号：US5805513A

公开(公告)日：1998-09-08

申请号：US432867

申请日：1995-05-02

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

公开(公告)号：US5790459A

公开(公告)日：1998-08-04

申请号：US781427

申请日：1997-01-10

申请人： Frankie F. Roohparvar

发明人： Frankie F. Roohparvar

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C29/46 ,  G11C29/50 ,  G11C16/06

CPC分类号： G11C29/50004 ,  G11C16/08 ,  G11C16/12 ,  G11C29/46 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04

摘要： An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true V.sub.th measurement test implemented by such circuit The memory circuit includes circuitry for implementing a true V.sub.th measurement test mode in which an external voltage (or a sequence of external voltages) is applied to an external pad, and a test voltage at least substantially equal to such external voltage (or a sequence of test voltages, each at least substantially equal to one of a sequence of external voltages) is applied directly to the control gates of all or selected ones of rows of the cells (e.g., to all or selected ones of the wordlines of the array). In preferred embodiments, each memory cell is a nonvolatile memory cell such as a flash memory cell. In preferred embodiments, the memory circuit includes circuitry for allowing application (directly, to the control gates) of test voltages having a broad range of selected values, including values much greater than and values much less than the memory circuit's internal supply voltage. In accordance with the invention, a memory circuit can operate in true V.sub.th measurement test modes in which a test voltage substantially equal to the external voltage is applied to the control gates of selected ones of the cells, and the cells are read using the same circuitry (e.g., a sense amplifier) that would be used to execute a normal read operation. The external voltage can be specially selected to have a value (or sequence of values) appropriate for performing any of a variety of tests on the cells.

摘要翻译： 一种具有存储器单元阵列并且可在至少一个测试模式以及正常工作模式下操作的集成存储器电路以及由这种电路实现的真正的Vth测量测试存储器电路包括用于实现真正的Vth测量的电路 测试模式，其中将外部电压（或外部电压序列）施加到外部焊盘，以及至少基本上等于该外部电压的测试电压（或测试电压序列，每个至少基本上等于 一系列外部电压）直接施加到单元格行的所有或选定行的控制栅极（例如，到阵列的所有或选定的字线）。 在优选实施例中，每个存储器单元是诸如闪存单元的非易失性存储器单元。 在优选实施例中，存储器电路包括用于允许（直接到控制栅极）应用具有宽范围选定值的测试电压的电路，其包括远大于和远低于存储器电路的内部电源电压的值。 根据本发明，存储器电路可以在真实的Vth测量测试模式下操作，其中基本上等于外部电压的测试电压被施加到所选择的单元的控制栅极，并且使用相同的电路读取单元 （例如，读出放大器），用于执行正常读取操作。 可以特别选择外部电压以具有适合于对电池执行各种测试的值（或值序列）。

公开(公告)号：US5774472A

公开(公告)日：1998-06-30

申请号：US866369

申请日：1997-05-30

申请人： Hideto Matsuoka

发明人： Hideto Matsuoka

IPC分类号： G11C29/12 ,  G11C29/26 ,  G11C29/46 ,  G11C29/48 ,  G06F11/00

CPC分类号： G11C29/12 ,  G11C29/46 ,  G11C29/48 ,  G11C29/26

摘要： In a semiconductor memory device, in a normal operation, data is written to selected four memory cells in accordance with external write data DQ0 to DQ3 applied to four data input/output terminals. In test mode, same data is commonly written to the selected four memory cells in accordance with write data DQ applied to one data input/output terminal. In the test mode operation, signal transmission between the remaining three data input/output terminals and the corresponding input buffer circuits is cut off by a CMOS logic gate provided therebetween and controlled in accordance with a test mode designating signal /TE.

摘要翻译： 在半导体存储器件中，在正常操作中，根据应用于四个数据输入/输出端子的外部写入数据DQ0至DQ3将数据写入所选择的四个存储器单元。 在测试模式下，根据应用于一个数据输入/输出端的写入数据DQ，相同的数据通常写入所选择的四个存储单元。 在测试模式操作中，剩余的三个数据输入/输出端子与相应的输入缓冲电路之间的信号传输被设置在其间的CMOS逻辑门切断，并根据测试模式指定信号/ TE进行控制。

公开(公告)号：US5751641A

公开(公告)日：1998-05-12

申请号：US579008

申请日：1995-12-27

申请人： Gianluca Petrosino

发明人： Gianluca Petrosino

IPC分类号： G06F11/22 ,  G11C29/46 ,  G11C7/00

CPC分类号： G06F11/22 ,  G11C29/46

摘要： A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.

摘要翻译： 公开了一种用于测试微处理器或微计算机的片上存储器的电路和方法。 存储器测试电路包括用于控制测试过程的输入寄存器，输出寄存器，加法器和定序器。 该过程包括从控制单元接收简单的通信协议以开始测试，运行诸如检查板，AAAAh，5555h等的公共存储器测试，然后将测试结果存储在输出寄存器中。 测试电路可以包括用于在微处理器或微型计算机运行其存储器测试时禁用系统的双向RESET信号装置。

公开(公告)号：US5745499A

公开(公告)日：1998-04-28

申请号：US540915

申请日：1995-10-11

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C29/46 ,  G01R31/28

CPC分类号： G11C29/46

摘要： An integrated memory circuit is described which can be tested using both a burn-in test and an application specific test. The application specific test is initiated by providing a supervoltage on one of the integrated memory circuit external input pins. A reference voltage circuit is described for producing a variable or multi-level reference voltage used by a supervoltage detection circuit. If a burn-in test is being performed, the reference voltage is adjusted from a level used when the memory is not operating in a burn-in test mode. A multi-level reference voltage is provided to the supervoltage detection circuit, thereby, adjusting the supervoltage level needed to initiate an application specific test.

公开(公告)号：US5745415A

公开(公告)日：1998-04-28

申请号：US734064

申请日：1996-10-18

申请人： Kenneth W. Marr

发明人： Kenneth W. Marr

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/00 ,  G11C11/413 ,  G11C29/06 ,  G11C29/14 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/46 ,  G11C29/50 ,  G11C11/41 ,  G11C2029/5004

摘要： A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.

公开(公告)号：US5668643A

公开(公告)日：1997-09-16

申请号：US653918

申请日：1996-05-28

申请人： Masaki Sakamoto ,  Yuki Oishi ,  Hideki Yorozu ,  Kazutaka Suzuki

发明人： Masaki Sakamoto ,  Yuki Oishi ,  Hideki Yorozu ,  Kazutaka Suzuki

IPC分类号： G11C29/46 ,  H04N1/41 ,  H04N1/403 ,  H04N1/407

CPC分类号： H04N1/41 ,  G11C29/46

摘要： A reading apparatus and a recording apparatus having the reading apparatus which can reduce storage capacity for storing read data and, because the read data processing modes can be switched according to the type of documents to be processed, perform fast and proper document reading operation. If a document to be processed is an image document, the controller operates in the image processing mode in which M pieces of read data are sampled out of N pieces of read data and a mean value of the M pieces of read data is calculated to be stored in the memory as gradation data of one pixel. If the document is a text document, the controller operates in the text processing mode in which read data of one read unit of the image scanner is digitized by a threshold to be stored in the memory. Switching between these two processing modes is performed by the conversion processing operator section in the controller.

摘要翻译： 具有能够减少用于存储读取数据的存储容量的读取装置的读取装置和记录装置，并且由于可以根据要处理的文档的类型切换读取的数据处理模式，因此执行快速且适当的文件读取操作。 如果要处理的文档是图像文档，则控制器在以N个读取数据中对M个读取数据进行采样的图像处理模式中操作，并且将M个读取数据的平均值计算为 存储在存储器中作为一个像素的灰度数据。 如果文档是文本文档，则控制器以文本处理模式操作，其中图像扫描器的一个读取单元的读取数据被阈值数字化以存储在存储器中。 在这两种处理模式之间切换由控制器中的转换处理操作部执行。

公开(公告)号：US5666314A

公开(公告)日：1997-09-09

申请号：US432723

申请日：1995-06-06

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任何一个有缺陷时，选择2K字线以外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US5661690A

公开(公告)日：1997-08-26

申请号：US607708

申请日：1996-02-27

申请人： Frankie Roohparvar

发明人： Frankie Roohparvar

IPC分类号： G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C16/04 ,  G11C2029/5004 ,  G11C29/46

摘要： An integrated memory circuit (chip) and methods for testing the chip. The chip has an array of memory cells, a sense amplifier for reading selected ones of the cells, and a switch having a first state allowing an external device connected to an external pad to sink a reference current from the sense amplifier and a second state disconnecting the pad from the sense amplifier (so that an internally generated reference current can be supplied to the sense amplifier with the switch in the second state). In the first state, the switch preferably is tolerant of a broad and continuous range of voltages on the pad. In some test modes, cells are read using a sense amplifier of the chip while selected voltages are applied to each cell and external equipment sinks reference current flowing from the sense amplifier through an external pad, thus sensing data from each cell with all the timing constraints usually placed on a read of the cell in the normal mode. In one test mode, all wordlines of the array are disabled and a read cycle is performed to measure all columns of the array sequentially while an external reference current flows between external test equipment and a sense amplifier used for performing the read cycle, and the sense amplifier output indicates whether one or more of the columns has leaky cells.

摘要翻译： 集成存储器电路（芯片）和芯片测试方法。 芯片具有存储单元阵列，用于读取选定单元的读出放大器，以及具有允许连接到外部焊盘的外部设备从读出放大器吸收参考电流的第一状态的开关和第二状态断开 来自读出放大器的焊盘（使得内部产生的参考电流可以被提供给具有第二状态的开关的读出放大器）。 在第一状态下，开关优选地容忍焊盘上的广泛且连续的电压范围。 在一些测试模式下，使用芯片的读出放大器读取单元，同时将选择的电压施加到每个单元，并且外部设备通过外部焊盘吸收从读出放大器流出的参考电流，从而以所有时序约束感测来自每个单元的数据 通常放置在正常模式下的单元读取。 在一个测试模式中，阵列的所有字线被禁用，并且执行读周期以顺序测量阵列的所有列，而外部参考电流在外部测试设备和用于执行读周期的读出放大器之间流动 放大器输出指示一个或多个列是否有泄漏单元。