公开(公告)号：US20010054717A1

公开(公告)日：2001-12-27

申请号：US09885943

申请日：2001-06-22

申请人： SHOWA DENKO K.K

发明人： Takashi Udagawa

IPC分类号： H01L027/15 ,  H01L031/12 ,  H01L033/00 ,  H01L029/80

CPC分类号： H01L33/32 ,  H01L33/007 ,  H01L33/0075

摘要： A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.

摘要翻译： 通过消除与衬底晶体的晶格失配和使用具有优异结晶度的氮化镓磷化物系发光结构而获得的高发光强度III族氮化物半导体发光器件。 基于磷化硅（BP）的缓冲层，在基板上形成氮化镓系磷化物系多层发光结构体。 基于磷化硼的缓冲层优选在低温下生长并呈现非晶形，以消除与衬底晶体的晶格失配。 在形成无定形缓冲层之后，逐渐转变为结晶层，以制造发光器件，同时保持与氮化镓基磷光体基发光部分的晶格匹配。

公开(公告)号：US20010046741A1

公开(公告)日：2001-11-29

申请号：US09894195

申请日：2001-06-27

发明人： Alan R. Reinberg

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L021/336 ,  H01L021/8234 ,  H01L029/80 ,  H01L031/112 ,  H01L029/76

CPC分类号： H01L21/823456 ,  H01L21/823487

摘要： A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear. The first and second channel lengths have different total lengths, both of the straight linear portions of the first and second channel lengths are angled from the plane, and at least one of the straight linear portions of the first and second channel lengths are beveled relative to the plane.

摘要翻译： 限定至少两个不同的场效应晶体管沟道长度的方法包括在衬底上形成沟道限定层，该半导体衬底具有沿平面延伸的平均全局外表面。 第一和第二开口被蚀刻到沟道限定层中。 第一和第二开口分别具有一对相对的侧壁，其具有与该平面成一定角度的基本上直的线性段。 与第二开口的相对侧壁的直线段相比，第一开口的相对侧壁的直线段相对于该平面的角度不同，因此具有不同的长度。 集成电路包括第一场效应晶体管和第二场效应晶体管。 第一和第二场效应晶体管具有沿其栅极介电层限定的各自的沟道长度，并且分别具有基本上直线性的至少一些部分。 第一和第二通道长度具有不同的总长度，第一和第二通道长度的直线部分的两个直线从平面成角度，并且第一和第二通道长度的直线部分中的至少一个相对于 飞机。

公开(公告)号：US20040218341A1

公开(公告)日：2004-11-04

申请号：US10428168

申请日：2003-04-30

发明人： Eric T. Martin ,  Mark Hunter ,  Arthur Piehl ,  James R. Przybyla ,  Matthew Gelhaus ,  Leslie Louis Szepesi JR.

IPC分类号： H01L029/80

CPC分类号： G02B26/001 ,  G09G3/3466 ,  G09G2300/0809 ,  H01G5/16

摘要： A charge control circuit for controlling a micro-electromechanical system (MEMS) device having variable capacitor formed by first conductive plate and a second conductive plate separated by a variable gap distance. The charge control circuit comprises a switch circuit configured to receive a reference voltage having a selected voltage level and configured to respond to an enable signal having a duration at least as long as an electrical time constant constant of the MEMS device, but shorter than a mechanical time constant of the MEMS device, to apply the selected voltage level across the first and second plates for the duration to thereby cause a stored charge having a desired magnitude to accumulate on the variable capacitor, wherein the variable gap distance is a function of the magnitude of the stored charge.

摘要翻译： 一种用于控制具有由第一导电板形成的可变电容器和由可变间隙距离分开的第二导电板的微机电系统（MEMS）装置的充电控制电路。 充电控制电路包括开关电路，其被配置为接收具有所选电压电平的参考电压并且被配置为响应具有至少等于MEMS器件的电时间常数常数的持续时间的使能信号，但是短于机械 时间常数，以在所述持续时间内在所述第一和第二板上施加所选择的电压电平，从而使具有期望幅度的存储电荷累积在所述可变电容器上，其中所述可变间隙距离是幅度的函数 的存储费用。

公开(公告)号：US20040206989A1

公开(公告)日：2004-10-21

申请号：US10606755

申请日：2003-06-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Hironori Yoshioka ,  Wataru Saito

IPC分类号： H01L029/80 ,  H01L031/112 ,  H01L031/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7802

摘要： A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first conductivity type formed from the surface of the semiconductor layer toward the semiconductor substrate and adjacently to the first impurity diffusion layer; a base layer of a second conductivity type selectively formed on each surface layer of the junction pairs which are formed in the first region, so as to connect with the first impurity diffusion layer and the second impurity diffusion layer in the same manner; a source layer of a first conductivity type selectively formed on each surface layer of the base layers of the second conductive type; a control electrode formed above each surface of the base layers and above each surface of the source layers via an insulating film; a first main electrode formed so as to cover the control electrode and to contact the source layers and the base layers in the same manner; and a second main electrode formed on a second main surface opposite to the first main surface of the semiconductor substrate.

摘要翻译： 半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的第一导电类型的半导体层，所述半导体层包括用于单元部分的第一区域和用于端接部分的第二区域，所述第二区域位于所述半导体衬底的外周中 第一区域，终端部分通过延伸耗尽层来缓和电场来保持击穿电压; 在半导体层中平行于第一主表面的第一方向上并且具有相互相反的导电类型的杂质的周期性地布置以便形成从第一区域到第二区域的线的结对对， 由半导体层的朝向半导体衬底的表面形成的第二导电类型的第一杂质扩散层和由半导体层的表面朝向半导体衬底形成的第一导电类型的第二杂质扩散层，并且相邻于 第一杂质扩散层; 选择性地形成在形成在第一区域的结对的每个表面层上的第二导电类型的基底层，以与第一杂质扩散层和第二杂质扩散层相同的方式连接; 选择性地形成在第二导电类型的基底层的每个表面层上的第一导电类型的源极层; 控制电极，其经由绝缘膜形成在所述基底层的每个表面上方和所述源极层的每个表面上方; 形成为覆盖控制电极并以相同的方式接触源极层和基极层的第一主电极; 以及形成在与所述半导体衬底的所述第一主表面相对的第二主表面上的第二主电极。

公开(公告)号：US20040188723A1

公开(公告)日：2004-09-30

申请号：US10818820

申请日：2004-04-06

发明人： Minoru Sugawara ,  Takashi Noguchi

IPC分类号： H01L029/80

CPC分类号： H01L21/823892 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/802

摘要： Disclosed is a semiconductor device capable of increasing the operational speed and reducing the power consumption. The semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor which are provided on a common base-substrate. A surface region, in which the n-channel field effect transistor is provided, of the base-substrate includes: a silicon substrate; a buffer layer formed on the silicon substrate, the buffer layer being made from a silicon-germanium compound having a germanium concentration gradually increased toward an upper surface of the buffer layer; a relax layer formed on the buffer layer, the relax layer being made from a silicon-germanium compound having a germanium concentration nearly equal to that of a surface portion of the buffer layer; and a silicon layer formed on the relax layer. Source/drain regions are formed in the silicon layer. A surface region, on which the p-channel field effect transistor is provided, of the base-substrate, includes: the silicon substrate; a silicon-germanium compound layer formed on the silicon substrate; and a cap layer formed on the silicon-germanium compound layer, the cap layer being made from silicon.

摘要翻译： 公开了能够提高操作速度并降低功耗的半导体器件。 半导体器件包括设置在公共基底基板上的n沟道场效应晶体管和p沟道场效应晶体管。 基底衬底的设置有n沟道场效应晶体管的表面区域包括：硅衬底; 形成在所述硅衬底上的缓冲层，所述缓冲层由锗浓度从所述缓冲层的上表面逐渐增加的硅锗化合物制成; 形成在所述缓冲层上的松弛层，所述弛豫层由锗浓度与所述缓冲层的表面部分的锗浓度几乎相等的硅锗化合物制成; 以及形成在松弛层上的硅层。 源极/漏极区域形成在硅层中。 基底衬底上设置有p沟道场效应晶体管的表面区域包括：硅衬底; 形成在硅衬底上的硅 - 锗化合物层; 以及形成在所述硅 - 锗化合物层上的覆盖层，所述盖层由硅制成。

公开(公告)号：US20040171240A1

公开(公告)日：2004-09-02

申请号：US10796514

申请日：2004-03-09

发明人： John P. Snyder ,  John M. Larson

IPC分类号： H01L021/336 ,  H01L021/28 ,  H01L031/112 ,  H01L029/80 ,  H01L021/44 ,  H01L021/8234

CPC分类号： H01L21/28194 ,  H01L21/26513 ,  H01L21/28167 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/095 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

摘要翻译： 本发明涉及一种用于通过高介电常数栅极绝缘层和形成具有衬底的肖特基接触或肖特基状区域的源极和/或漏极来调节电流的装置及其制造方法。 在一个方面，栅极绝缘层的介电常数大于硅的介电常数。 在另一方面，电流调节装置可以是具有任何取向的MOSFET器件，可选地是平面P型或N型MOSFET。 在另一方面，源极和/或漏极可部分或全部由硅化物组成。

公开(公告)号：US20040124446A1

公开(公告)日：2004-07-01

申请号：US10334195

申请日：2002-12-28

发明人： Wilmer F. Borger ,  Jeffrey T. West ,  Ebrahim Andideh

IPC分类号： H01L029/80 ,  H01L031/112 ,  H01L021/31

CPC分类号： H01L21/0214 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/7682

摘要： A series of conductive layers separated by interlayer gaps is formed adjacent a substrate layer, the conductive layer and interlayer gap dimensions defining aspect ratios for trenches between the conductive layers. A layer of dielectric material is deposited over the conductive layers using plasma enhanced chemical vapor deposition. Trenches having aspect ratios within specified geometric categories are incompletely filled, leaving interlayer voids which may have desirable dielectric properties.

摘要翻译： 在衬底层附近形成由层间间隔分开的一系列导电层，导电层和层间间隙尺寸限定导电层之间沟槽的纵横比。 使用等离子体增强化学气相沉积在导电层上沉积介电材料层。 具有特定几何类别的长宽比的沟槽不完全填充，留下可能具有所需介电特性的层间空隙。

公开(公告)号：US20040124445A1

公开(公告)日：2004-07-01

申请号：US10713054

申请日：2003-11-17

发明人： Masanobu Ogino ,  Yoshikatsu Suto ,  Yoshiro Baba

IPC分类号： H01L021/332 ,  H01L029/80 ,  H01L031/112 ,  C30B001/00

CPC分类号： H01L29/06 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2205 ,  H01L21/2256 ,  H01L29/78

摘要： A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.

摘要翻译： 公开了一种半导体衬底，其包括含有低浓度杂质的轻掺杂衬底，重掺杂扩散层，形成在轻掺杂衬底的顶部上，杂质浓度高于轻掺杂衬底， 外延层，其形成在重掺杂扩散层的顶部上，并且含有比重掺杂扩散层低的浓度的杂质。

公开(公告)号：US20040124443A1

公开(公告)日：2004-07-01

申请号：US10735759

申请日：2003-12-16

申请人： Murata Manufacturing Co., Ltd.

发明人： Kazuhiro Yoshida

IPC分类号： H01L029/80

CPC分类号： H01L29/66871 ,  H01L27/0629 ,  H01L27/095

摘要： A method for efficiently manufacturing a semiconductor device, the semiconductor device having an FET and a pn junction diode provided on the same semiconductor substrate, the FET having a Schottky junction for a gate electrode and a gate recess, includes the steps of forming a channel layer, a first etching stopper layer, an n-type common layer, a second etching stopper layer, a p-type layer, and a third etching stopper layer on the semiconductor substrate in that order; etching away the p-type layer and the third etching stopper layer in specific regions; simultaneously forming a source electrode, a drain electrode, a cathode; forming a mask having an opening for forming a gate recess and a gate electrode and an opening for forming an anode; forming the gate recess by etching while the third etching stopper layer prevents the p-type layer from being etched; and simultaneously forming the gate electrode and the anode.

摘要翻译： 一种用于有效制造半导体器件的方法，具有设置在同一半导体衬底上的FET和pn结二极管的半导体器件，具有用于栅极电极的肖特基结和FET栅极的FET包括以下步骤：形成沟道层 ，在半导体衬底上的第一蚀刻停止层，n型公共层，第二蚀刻停止层，p型层和第三蚀刻停止层; 在特定区域蚀刻掉p型层和第三蚀刻阻挡层; 同时形成源电极，漏电极，阴极; 形成具有用于形成栅极凹部的开口和用于形成阳极的栅电极和开口的掩模; 通过蚀刻形成栅极凹槽，同时第三蚀刻停止层防止p型层被蚀刻; 并同时形成栅电极和阳极。

公开(公告)号：US20040113239A1

公开(公告)日：2004-06-17

申请号：US10321874

申请日：2002-12-17

申请人： Intel Corporation

发明人： Victor Prokofiev ,  Henning Braunisch

IPC分类号： H01L029/80 ,  H01L031/112 ,  H01L039/00

CPC分类号： H01L23/66 ,  H01L23/48 ,  H01L23/5225 ,  H01L24/81 ,  H01L24/85 ,  H01L2223/6627 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.

摘要翻译： 无接触式高速信号接口和方法提供跨接口的高速信号的通信，诸如管芯基板接口或管芯接口。 该接口包括布置在电介质上以传送高速正向入射信号的传输线结构，以及另一传输线结构，其设置在另一介质介质上并基本上与另一传输线结构对准， 速度信号在与入射信号相反的方向上。