公开(公告)号：US09606085B2

公开(公告)日：2017-03-28

申请号：US14027940

申请日：2013-09-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto Pagani

IPC: G01R33/12 ,  G01R33/18 ,  G01N27/72 ,  G01N33/38 ,  G01N27/82

CPC classification number: G01N27/82 ,  G01N27/72 ,  G01N33/381 ,  G01N33/383 ,  Y10T29/49018 ,  Y10T29/4902

Abstract: A building structure includes a block of building material and a magnetic circuit buried in the block of building material. The structure also includes a plurality of sensing devices buried in the block of building material. Each sensing device may include a contactless power supplying circuit magnetically coupled with the magnetic circuit to generate a supply voltage when the magnetic circuit is subject to a variable magnetic field.

公开(公告)号：US20170085180A1

公开(公告)日：2017-03-23

申请号：US15087082

申请日：2016-03-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Paolo Pulici ,  Massimo Mazzucco

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/1584 ,  G05F1/46 ,  H02M1/08 ,  H02M3/156 ,  H02M2001/0025 ,  H02M2001/008

Abstract: A method manages hysteretic DC-DC buck converters each including a hysteretic comparator operating according to a respective hysteresis window. The method includes, in a given converter, verifying if a respective feedback voltage reaches a lower threshold in order to enter a switch-on period of the converter, The method comprises: while the verifying indicates that the lower threshold is not reached, detecting if another converter has entered a respective switch on period and, in the affirmative, entering a hysteresis voltage adjustment procedure, include increasing by a given amount the amplitude of the hysteresis window of the given converter by reducing the lower threshold of the hysteresis window.

公开(公告)号：US20170074914A1

公开(公告)日：2017-03-16

申请号：US15070509

申请日：2016-03-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Riccardo Condorelli ,  Daniele Mangano

IPC: G01R27/26

CPC classification number: G01R27/26 ,  G01D5/20 ,  H03K17/9537 ,  H03K17/954

Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.

Abstract translation: 在一个实施例中，电感/ LC传感器装置包括：用于累积激发能量的能量存储装置，LC传感器，其被配置为使用积聚在能量存储装置中并传送到LC传感器的能量进行振荡;能量检测器，用于检测累积的能量 在所述能量存储装置中达到充电阈值，以及至少一个与所述能量检测器耦合的开关，用于当所述能量检测器已经达到所述充电阈值时终止在所述能量存储装置中累积激发能量。

公开(公告)号：US20170073220A1

公开(公告)日：2017-03-16

申请号：US15074755

申请日：2016-03-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Enri DUQI ,  Sebastiano CONTI

IPC: B81B7/00

CPC classification number: B81B7/0054 ,  B81B3/0051 ,  B81B7/0048 ,  B81B7/008 ,  B81B2201/0264 ,  B81C1/00325 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A MEMS device is provided with: a supporting base, having a bottom surface in contact with an external environment; a sensor die, which is of semiconductor material and integrates a micromechanical detection structure; a sensor frame, which is arranged around the sensor die and is mechanically coupled to a top surface of the supporting base; and a cap, which is arranged above the sensor die and is mechanically coupled to a top surface of the sensor frame, a top surface of the cap being in contact with an external environment. The sensor die is mechanically decoupled from the sensor frame.

Abstract translation: MEMS装置设置有：支撑基座，其具有与外部环境接触的底面; 传感器芯片，其是半导体材料并且集成了微机械检测结构; 传感器框架，其布置在所述传感器模具周围并且机械地联接到所述支撑基座的顶表面; 以及盖，其布置在传感器模具的上方并且机械地联接到传感器框架的顶表面，盖的顶表面与外部环境接触。 传感器模具与传感器框架机械分离。

公开(公告)号：US09595946B2

公开(公告)日：2017-03-14

申请号：US14592364

申请日：2015-01-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco Raimondi ,  Edoardo Botti

IPC: H03K5/01 ,  H03F1/26 ,  H03F1/32 ,  H03F3/217 ,  H03K7/08

CPC classification number: H03K5/1252 ,  H03F1/26 ,  H03F1/32 ,  H03F3/217 ,  H03K4/08 ,  H03K5/01 ,  H03K7/08

Abstract: A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.

Abstract translation: 一种方法是从影响调制信号输入到脉冲宽度调制（PWM）调制器的积分器的特性以及用于产生PWM调制器的三角形波形的方波载波信号的特性减少脉冲跳跃。 该方法可以包括在由积分器输出的三角波形的顶点处创建宽同步峰。

公开(公告)号：US20170062055A1

公开(公告)日：2017-03-02

申请号：US15140770

申请日：2016-04-28

Applicant: STMicroelectronics S.r.l

Inventor： Salvatore Polizzi ,  Giovanni Campardo

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract translation: 非易失性存储器件包括具有以字线布置并接收电源电压的存储器单元的存储器阵列。 行解码器包括输入和预解码模块，其被配置为在电源电压范围内接收地址信号并产生低电压的预解码地址信号。 驱动模块被配置为产生偏置信号，用于在高电压和高于电源的升压电压的范围内从作为预解码地址信号的函数的解码的地址信号开始偏置存储器阵列的字线 电压。 处理模块被配置为接收预解码的地址信号，并共同执行逻辑组合的操作和用于生成解码的地址信号的预解码的地址信号的升压的操作。

公开(公告)号：US09577582B2

公开(公告)日：2017-02-21

申请号：US14512704

申请日：2014-10-13

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Botti

IPC: H03F3/217 ,  H03F1/04 ,  H03F1/02

CPC classification number: H03F1/0233 ,  H03F1/0205 ,  H03F3/2171 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/171 ,  H03F2200/267 ,  H03F2200/351 ,  H03F2200/471

Abstract: A method is for reducing power dissipation in a switching amplifier. The method may include comparing a load current with a ripple current and, if the load current is greater than the ripple current, then detecting a first potential value at a first output terminal of the switching amplifier, detecting a second potential value at a second output terminal of the switching amplifier, detecting a third potential value between first and the second terminals of a first capacitor, and coupling the first terminal of the first capacitor to one of the first output terminal and the second output terminal. The second terminal of the first capacitor may be coupled to a reference voltage, the first output terminal, or the second output terminal based upon whether the first potential value or the second potential value is equal to the third potential value.

Abstract translation: 一种用于降低开关放大器功耗的方法。 该方法可以包括将负载电流与纹波电流进行比较，并且如果负载电流大于纹波电流，则检测开关放大器的第一输出端处的第一电位值，在第二输出端检测第二电位值 端子，检测第一电容器的第一和第二端子之间的第三电位值，并将第一电容器的第一端子耦合到第一输出端子和第二输出端子之一。 基于第一电位值或第二电位值是否等于第三电位值，第一电容器的第二端子可以耦合到参考电压，第一输出端子或第二输出端子。

公开(公告)号：US09571398B2

公开(公告)日：2017-02-14

申请号：US14080080

申请日：2013-11-14

Applicant: STMicroelectronics S.R.L.

Inventor： Danilo Pietro Pau

IPC: H04L12/801 ,  H04N19/115 ,  H04N19/164 ,  H04N19/17 ,  G06K9/46 ,  G06F17/30

CPC classification number: H04N19/115 ,  G06F17/30799 ,  G06K9/4671 ,  H04L47/12 ,  H04N19/146 ,  H04N19/164 ,  H04N19/17 ,  H04N19/172 ,  H04N19/196

Abstract: In an embodiment, digital video frames in a flow are subjected to a method of extraction of features including the operations of: extracting from the video frames respective sequences of pairs of keypoints/descriptors limiting to a threshold value the number of pairs extracted for each frame; sending the sequences extracted from an extractor module to a server for processing with a bitrate value variable in time; receiving the aforesaid bitrate value variable in time at the extractor as target bitrate for extraction; and limiting the number of pairs extracted by the extractor to a threshold value variable in time as a function of the target bitrate.

Abstract translation: 在一个实施例中，流程中的数字视频帧经受提取特征的方法，包括以下操作：从视频帧中提取相应的关键点/描述符序列，限制阈值，为每个帧提取的对数 ; 将从提取器模块提取的序列发送到服务器，以便在时间上以比特率值变量进行处理; 以提取器的时间接收上述比特率值变量作为提取的目标比特率; 并且将提取器提取的对数量作为目标比特率的函数在时间上限制为阈值变量。

公开(公告)号：US20170040244A1

公开(公告)日：2017-02-09

申请号：US15076754

申请日：2016-03-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fulvio Vittorio FONTANA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/4832 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method may include providing an electrically conductive laminar base member having a die attachment portion and a lead frame portion, producing a distribution of holes opening at a front surface of the base member, attaching an integrated circuit onto the front surface of the base member at the attachment portion, and producing a wire bonding pattern between the integrated circuit and wire bonding locations on the front surface of the base member at the lead frame portion. An electrically insulating package molding compound may be molded onto the front surface of the base member so that the integrated circuit and the wire bonding pattern are embedded in the package molding compound which penetrates into the holes opening at the front surface of the base member. The base member may be selectively etched from its back surface to produce residual portions of the base member at the wire bonding locations.

Abstract translation: 一种方法可以包括提供具有管芯附接部分和引线框架部分的导电层状基底构件，产生在基底构件的前表面处开口的孔的分布，将集成电路附接到基底构件的前表面上 并且在引线框架部分处在基底构件的前表面上的集成电路和引线接合位置之间产生引线键合图案。 电绝缘包装模塑料可以模制到基底构件的前表面上，使得集成电路和引线接合图案嵌入到穿入基体前表面的孔中的封装模塑料中。 可以从其背面选择性地蚀刻基底构件，以在引线接合位置产生基底构件的残留部分。

公开(公告)号：US09565506B2

公开(公告)日：2017-02-07

申请号：US14532960

申请日：2014-11-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco Veneri ,  Alessandro Morcelli

IPC: H04R29/00 ,  H04R3/00

CPC classification number: H04R29/004 ,  H04R3/00 ,  H04R3/005 ,  H04R29/005

Abstract: An interface for expanding a signal starting from a first sensing signal and a second sensing signal, wherein a receiving intensity measuring element generates an intensity signal; and a selector is controlled to select each time the first sensing signal, the second sensing signal, or a combined signal deriving from a weighted combination of these signals. The selector uses a plurality of thresholds variable as a function of the intensity signal.

Abstract translation: 一种用于从第一感测信号和第二感测信号开始扩展信号的接口，其中接收强度测量元件产生强度信号; 并且控制选择器以每次选择第一感测信号，第二感测信号或从这些信号的加权组合导出的组合信号。 选择器使用多个阈值作为强度信号的函数而变化。