公开(公告)号：US09496884B1

公开(公告)日：2016-11-15

申请号：US15076338

申请日：2016-03-21

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Nanda Govind Jayaraman

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/1023 ,  H03M1/00 ,  H03M1/12 ,  H03M1/361

Abstract: System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

Abstract translation: 基于ADC的数字输出，在背景中校准ADC中替代比较器的直流偏移的系统和方法。 与多个样本的A / D转换并行，校准逻辑使用两个计数器来分别表示落入第一模拟范围和第二模拟范围的采样的ADC输出的出现。 两个范围对称关于MSB参考电压，并且组合覆盖该位的标称电压范围。 基于两个计数之间的差和两个计数的和的比率导出DC偏移。 校准逻辑可以可选地校准比较器。 可以基于与其相关联的各种位置来连续校准每个比较器。

公开(公告)号：US09372500B2

公开(公告)日：2016-06-21

申请号：US14191923

申请日：2014-02-27

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Ayush Goyal ,  Phil Mitchell

IPC: H04L1/00 ,  G06F15/173 ,  G06F1/04

CPC classification number: G06F1/04 ,  G06F11/0745 ,  G06F11/0757 ,  G06F13/4027

Abstract: Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.

Abstract translation: 各种方面提供了基于与数据请求相关联的时钟计数器生成超时信号。 接口组件被配置为从主设备接收数据请求并将数据请求转发到从设备。 超时组件被配置用于在接收到与来自从设备的数据请求相关联的数据响应之前响应于确定与时钟计数器相关联的阈值电平来保持与数据请求相关联的时钟计数器并产生超时信号 。

公开(公告)号：US20160170910A1

公开(公告)日：2016-06-16

申请号：US14566945

申请日：2014-12-11

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Tanmay Sunit Inamdar ,  Ravi Rajendra Patel

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1475 ,  G06F12/1036 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657 ,  H04L49/90 ,  H04L49/901

Abstract: Various aspects facilitate implementing a memory translation table associated with key-based indexing. A table component is configured for generating a memory translation table and a key component is configured for allocating a key associated with a memory access based on a virtual address and a set of access permissions. A descriptor component is configured for generating a descriptor associated with the memory translation table that comprises at least the set of access permissions and a portion of the key.

Abstract translation: 各方面有助于实现与基于键的索引相关联的存储器转换表。 配置表组件用于生成存储器转换表，并且密钥组件被配置为基于虚拟地址和一组访问许可来分配与存储器访问相关联的密钥。 描述符组件被配置用于生成与所述存储器转换表相关联的描述符，所述描述符包括至少所述一组访问许可和所述密钥的一部分。

公开(公告)号：US20150326197A1

公开(公告)日：2015-11-12

申请号：US14162896

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

IPC: H03G3/30

CPC classification number: H03G3/30 ,  H03G1/0029

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port

Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出

公开(公告)号：US20150324306A1

公开(公告)日：2015-11-12

申请号：US14162903

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Keyur Chudgar ,  Kumar Sankaran

IPC: G06F13/28

CPC classification number: G06F13/385

Abstract: Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Abstract translation: 各种实施例提供了芯片上的系统或执行流锁定的芯片上的系统，其中分组或分组流入队列到特定队列，其中每个队列与多处理器/多核系统中的相应核相关联或 服务器在芯片上。 对于分配给特定处理器的每个数据包流或流，芯片上的服务器可以并行地从同一个以太网接口的多个流处理和进入来自多个队列的数据包。 每个队列可以向其分配的处理器发出中断，从而允许每个处理器同时从其各自的队列接收数据包。 因此，通过为不同流并行接收和处理数据包，从而增加分组处理速度。

公开(公告)号：US20150324203A1

公开(公告)日：2015-11-12

申请号：US14203896

申请日：2014-03-11

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Matthew Ashcraft ,  Richard W. Thaik

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3806 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0875

Abstract: Various aspects provide for facilitating prediction of instruction pipeline hazards in a processor system. A system comprises a fetch component and an execution component. The fetch component is configured for storing a hazard prediction associated with a group of memory access instructions in a buffer associated with branch prediction. The execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of the hazard prediction entry. In an aspect, the hazard prediction entry is configured for predicting whether the group of memory access instructions is associated with an instruction pipeline hazard.

Abstract translation: 各方面提供了便于对处理器系统中的指令管线危险的预测。 系统包括获取组件和执行组件。 提取组件被配置用于存储与分支预测相关联的缓冲器中与一组存储器访问指令相关联的危险预测。 执行组件被配置为执行与该组存储器访问指令相关联的存储器访问指令作为危害预测条目的函数。 在一方面，危险预测条目被配置用于预测该组存储器访问指令是否与指令管道危险相关联。

公开(公告)号：US09065610B2

公开(公告)日：2015-06-23

申请号：US13865843

申请日：2013-04-18

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Timothy P. Walker

IPC: H03D3/24 ,  H04L25/49 ,  H04L1/00 ,  H03L7/081 ,  H04J3/07

CPC classification number: H04L1/004 ,  H03L1/00 ,  H03L7/081 ,  H03L7/107 ,  H03L2207/50 ,  H04J3/076

Abstract: Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

Abstract translation: 用于平滑由字节填充产生的抖动的系统和方法。 频率合成器包括与PLL耦合的平滑逻辑。 平滑逻辑被配置为将由相位频率检测器产生的相位误差信号修改成在多个时钟周期上分布的分布相位误差信号。 分布相位误差信号用于驱动DCO。 平滑逻辑可以包括斜坡逻​​辑，其可操作以产生一系列斜坡值来代替相位误差信号中的相位差。 相位差可对应于填充字节。

公开(公告)号：US09048930B2

公开(公告)日：2015-06-02

申请号：US13854675

申请日：2013-04-01

Applicant: Applied Micro Circuits Corporation

Inventor： Dariush Dabiri

IPC: H04B3/46

CPC classification number: H04B3/46 ,  H04B17/345

Abstract: One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference.

Abstract translation: 一个或多个处理单元被编程为在信号的频域表示中从M个音调中选择一组音调，其包括至少最强音（相对于背景噪声）和与其相邻的音调。 在信号的频域表示中的M个复数中，识别一组复数，并将其表示为对应于所选择的一组音调的向量Z。 然后将向量Z乘以预定的矩阵G的每个M列，以标识Z中的子分辨率最大值。由Z和G的矢量相乘产生的M个乘积至少用于确定和存储在存储器中 一个或两个：（A）指示信号中存在或不存在窄带干扰的标志; 和（B）对窄带干扰的频率的估计。

公开(公告)号：US20150150009A1

公开(公告)日：2015-05-28

申请号：US14090610

申请日：2013-11-26

Applicant: Applied Micro Circuits Corporation

Inventor： Dimitri MAVROIDIS

IPC: G06F9/48 ,  G06F9/52

CPC classification number: H04L47/10

Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.

Abstract translation: 凭借采用单处理核心逻辑的基于分组的时间分片，多信道信号处理的系统和方法。 处理核心逻辑被配置为在数据处理单元处从多个通信信道接收数据流，并且以时间分割方式处理数据流的数据片段。 处理核心逻辑可以从处理第一数据流的第一数据片段切换到在时间片段的末尾处理第二数据流的第一数据片段，其中所述时间片由与所述数据相关联的片段边界确定 第一个数据流的片段。

公开(公告)号：US09008255B1

公开(公告)日：2015-04-14

申请号：US14061307

申请日：2013-10-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Timothy P. Walker

IPC: H04L7/033

CPC classification number: H03L7/093 ,  H04J3/07

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract translation: 用于有效抖动缓解或从间隙信号中移除的系统和方法。 使用相位缓解模块来产生离散校正值，用于修改在有效信号和PLL的反馈信号之间检测的相位误差信号。 可以从与PLL相关联的相位频率检测器的输出中数字地减去校正值。 校正值的顺序可以基于输入信号和无抖动的目标反馈信号之间的相位差，并且具有等于输入信号的平均周期的周期来确定。 校正值的平均值基本上等于零，并且修正的相位误差信号的平均值基本上等于零。