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    METHOD FOR FABRICATING AN ISOLATION STRUCTURE
    81.
    发明申请
    METHOD FOR FABRICATING AN ISOLATION STRUCTURE 有权
    制造隔离结构的方法

    公开(公告)号：US20100255654A1

    公开(公告)日：2010-10-07

    申请号：US12753972

    申请日：2010-04-05

    Applicant: Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jung Lin, JR. ,  Yu Chao Lin ,  Chih-Han Lin

    Inventor： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jung Lin, JR. ,  Yu Chao Lin ,  Chih-Han Lin

    IPC: H01L21/762

    CPC classification number: H01L21/76232

    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.

    Abstract translation: 本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

    NOVEL SOLUTION FOR POLYMER AND CAPPING LAYER REMOVING WITH WET DIPPING IN HK METAL GATE ETCHING PROCESS
    82.
    发明申请
    NOVEL SOLUTION FOR POLYMER AND CAPPING LAYER REMOVING WITH WET DIPPING IN HK METAL GATE ETCHING PROCESS 有权
    用于聚合物和封盖层的新颖解决方案在HK METAL GATE ETCHING PROCESS

    公开(公告)号：US20100062590A1

    公开(公告)日：2010-03-11

    申请号：US12338615

    申请日：2008-12-18

    Applicant: Jr Jung Lin ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

    Inventor： Jr Jung Lin ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

    IPC: H01L21/4763 ,  H01L21/465

    CPC classification number: H01L21/28123 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/31111

    Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

    Abstract translation: 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括对衬底施加第一蚀刻工艺以去除衬底上的多晶硅层和金属栅极层; 将稀释的氢氟酸（HF）施加到基底以除去聚合物残渣; 然后用包括盐酸盐（HCl），过氧化氢（H 2 O 2）和水（H 2 O）的清洗溶液施加到基材上; 将稀释的盐酸盐（HCl）的湿蚀刻工艺施加到基底上以去除覆盖层; 以及通过第二蚀刻工艺施加到所述衬底以去除高k电介质材料层。

    Method for semiconductor device performance enhancement
    83.
    发明授权
    Method for semiconductor device performance enhancement 有权
    半导体器件性能提高的方法

    公开(公告)号：US07632729B2

    公开(公告)日：2009-12-15

    申请号：US11527616

    申请日：2006-09-27

    Applicant: Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    Inventor： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

    Abstract: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

    Abstract translation: 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

    HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    84.
    发明申请
    HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    高K介电金属栅组件结构及其形成方法

    公开(公告)号：US20090108365A1

    公开(公告)日：2009-04-30

    申请号：US11926830

    申请日：2007-10-29

    Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    IPC: H01L27/092 ,  H01L21/3205

    CPC classification number: H01L21/823857 ,  H01L21/823842

    Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.

    Abstract translation: 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。 用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂 具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

    Natural tourmaline anion fiber and filter and producing method
    86.
    发明申请
    Natural tourmaline anion fiber and filter and producing method 有权
    天然电气阴离子纤维和过滤器及其制备方法

    公开(公告)号：US20070259178A1

    公开(公告)日：2007-11-08

    申请号：US11416155

    申请日：2006-05-03

    Applicant: Ming-Fung Lin ,  Hung-Jen Chen ,  Chia-Jen Chen ,  Yung-Chien Chen ,  Chao-Mulan Chen

    Inventor： Ming-Fung Lin ,  Hung-Jen Chen ,  Chia-Jen Chen ,  Yung-Chien Chen ,  Chao-Mulan Chen

    IPC: B32B15/00

    CPC classification number: D01F1/103 ,  B01D39/1623 ,  B01D2239/0216 ,  B01D2239/0258 ,  B01D2239/0407 ,  D01F6/04 ,  D01F6/06 ,  D01F6/46 ,  Y10T428/2913 ,  Y10T428/2927 ,  Y10T428/294 ,  Y10T428/2967 ,  Y10T428/2969

    Abstract: The present invention provides to a method of producing fiber from tourmaline anion fiber; of which, polypropylene or polyethylene chip, TPE and submicrometer tourmaline particle are prepared and then rolled into submicrometer tourmaline agglomerate through granulation by double screw; then, take submicrometer tourmaline agglomerate and polypropylene or polyethylene chip, of which the content of tourmaline agglomerate accounts for 1˜10% of gross weight, and TPE for 1˜40% of gross weight; tourmaline agglomerate and polypropylene or polyethylene are melted into composite fiber or filter material via spinning, such that the fiber or filter material can yield anion and present outstanding gas permeability and mechanical property.

    Abstract translation: 本发明提供一种由电气石阴离子纤维生产纤维的方法; 其中制备聚丙烯或聚乙烯芯片，TPE和亚微米电气石颗粒，然后通过双螺杆粉碎成亚微米电气石团聚体; 然后采用亚微米电气石聚集体和聚丙烯或聚乙烯芯片，其中电气石聚集体含量占总重量的1〜10％，TPE占总重量的1〜40％; 电气石聚集体和聚丙烯或聚乙烯通过纺丝熔化成复合纤维或过滤材料，使得纤维或过滤材料可产生阴离子并具有优异的气体渗透性和机械性能。

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