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    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE
    81.
    发明申请
    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE 失效
    集成电路互连结构

    公开(公告)号：US20120264289A1

    公开(公告)日：2012-10-18

    申请号：US13531015

    申请日：2012-06-22

    Applicant: Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    Inventor： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    IPC: H01L21/768

    CPC classification number: H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

    Abstract translation: 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

    Integrated circuit interconnect structure
    82.
    发明授权
    Integrated circuit interconnect structure 有权
    集成电路互连结构

    公开(公告)号：US08237286B2

    公开(公告)日：2012-08-07

    申请号：US12760594

    申请日：2010-04-15

    Applicant: Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    Inventor： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    IPC: H01L23/522

    CPC classification number: H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

    Abstract translation: 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

    Test structure for determination of TSV depth
    83.
    发明授权
    Test structure for determination of TSV depth 有权
    用于测定TSV深度的测试结构

    公开(公告)号：US08232115B2

    公开(公告)日：2012-07-31

    申请号：US12566726

    申请日：2009-09-25

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H01L21/66

    CPC classification number: H01L22/34 ,  H01L21/76898

    Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

    Abstract translation: 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

    Method, structure, and design structure for a through-silicon-via Wilkinson power divider
    84.
    发明授权
    Method, structure, and design structure for a through-silicon-via Wilkinson power divider 有权
    通过硅片通过威尔金森功率分配器的方法，结构和设计结构

    公开(公告)号：US08216912B2

    公开(公告)日：2012-07-10

    申请号：US12548033

    申请日：2009-08-26

    Applicant: Hanyi Ding ,  Alvin J. Joseph ,  Wayne H. Woods, Jr.

    Inventor： Hanyi Ding ,  Alvin J. Joseph ,  Wayne H. Woods, Jr.

    IPC: H01L21/20 ,  H01L21/44

    CPC classification number: G06F17/5077 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P5/16 ,  H01P11/007 ,  H01L2924/00

    Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

    Abstract translation: 一种通过硅通孔威尔金森功率分配器的方法，结构和设计结构。 一种方法包括：在基板的第一侧上形成输入; 形成包括在所述基板中形成的第一穿通硅通孔的第一支脚，其中所述第一支路电连接所述输入端和第一输出端; 形成包括形成在所述基板中的第二通硅通孔的第二支脚，其中所述第二支脚电连接所述输入端和第二输出端，以及形成电连接在所述第一输出端和所述第二输出端之间的电阻器。

    Methods of fabricating coplanar waveguide structures
    86.
    发明授权
    Methods of fabricating coplanar waveguide structures 有权
    制造共面波导结构的方法

    公开(公告)号：US08028406B2

    公开(公告)日：2011-10-04

    申请号：US12061861

    申请日：2008-04-03

    Applicant: Hanyi Ding ,  Essam F. Mina ,  Guoan Wang ,  Wayne H. Woods

    Inventor： Hanyi Ding ,  Essam F. Mina ,  Guoan Wang ,  Wayne H. Woods

    IPC: H05K3/10 ,  H01P11/00 ,  H01P3/00

    CPC classification number: H01P11/003 ,  H01P3/003 ,  Y10T29/49016 ,  Y10T29/49155 ,  Y10T29/49162

    Abstract: Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.

    Abstract translation: 制造共面波导结构的方法。 该方法可以包括在第一和第二接地导体之间的共面布置中形成第一和第二接地导体和信号导体，在信号导体和第一和第二接地导体之上形成基本上平行的屏蔽导体的第一共面阵列，并形成 在信号导体和第一和第二接地导体下面的基本上平行的屏蔽导体的第二共面阵列。 该方法还包括形成位于信号导体和第一接地导体之间横向定位的第一多个导电桥，以及形成位于信号导体和第二接地导体之间横向定位的第二多个导电桥。 第一多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。 第二多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。

    Method of forming a high performance fet and a high voltage fet on a SOI substrate
    87.
    发明授权
    Method of forming a high performance fet and a high voltage fet on a SOI substrate 有权
    在SOI衬底上形成高性能fet和高电压fet的方法

    公开(公告)号：US08012814B2

    公开(公告)日：2011-09-06

    申请号：US12188366

    申请日：2008-08-08

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    IPC: H01L21/84

    CPC classification number: H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

    Abstract translation: 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

    Chip Inductor With Frequency Dependent Inductance
    88.
    发明申请
    Chip Inductor With Frequency Dependent Inductance 有权
    具有频率依赖电感的片式电感器

    公开(公告)号：US20100237464A1

    公开(公告)日：2010-09-23

    申请号：US12632030

    申请日：2009-12-07

    Applicant: Hanyi Ding ,  Wayne H. Woods, JR.

    Inventor： Hanyi Ding ,  Wayne H. Woods, JR.

    IPC: H01L27/06 ,  G06F17/50

    CPC classification number: H01L28/10 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/31053 ,  H01L21/76808 ,  H01L21/76826 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L29/432 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

    Abstract translation: 包括信号传输金属线和电容接地感应信号耦合金属线的一组金属线结构被嵌入在电介质材料层中。 电容器串联连接在电容接地的感应信号耦合金属线路和可能在输入侧或输出侧的局部电接地之间。 金属线结构和电容集合提供了一个频率相关的电感。 频率依赖电感器的Q因子具有多个峰值，使得能够在多个频率下操作频率相关的电感器。 可以在频率相关电感器中提供多个电容耦合的感应信号耦合金属线路，每个电路通过电容器连接到本地电接地。 通过选择电容器的不同电容值，可以在不同信号频率的频率相关电感器中获得Q因子的多个值。

    INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE
    89.
    发明申请
    INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE 有权
    集成的毫米波天线和基座上的收发器

    公开(公告)号：US20100035370A1

    公开(公告)日：2010-02-11

    申请号：US12187436

    申请日：2008-08-07

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

    IPC: H01L21/00

    CPC classification number: H01Q1/40 ,  H01Q9/28

    Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.

    Abstract translation: 提供集成收发器，天线和接收器的半导体芯片。 收发器形成在半导体衬底的前侧。 至少一个通过衬底通孔提供收发器和半导体衬底的背面之间的电连接。 连接到收发器的天线形成在前侧的电介质层中。 反射板与穿通基板连接，并形成在背面。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 通过衬底沟槽的阵列可以形成并填充介电材料，以减小天线和反射板之间的材料的有效介电常数，从而减小毫米波的波长并提高辐射效率。

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