利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

168 条记录 (耗时 0.066 秒)

    High-quality SGOI by oxidation near the alloy melting temperature
    81.
    发明授权
    High-quality SGOI by oxidation near the alloy melting temperature 有权
    高品质的SGOI通过氧化在合金熔化温度附近

    公开(公告)号：US07473587B2

    公开(公告)日：2009-01-06

    申请号：US11029921

    申请日：2005-01-05

    申请人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

    摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

    摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

    LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME
    82.
    发明申请
    LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME 有权
    低温电动活化门电极及其制造方法

    公开(公告)号：US20080203447A1

    公开(公告)日：2008-08-28

    申请号：US11678338

    申请日：2007-02-23

    申请人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： H01L29/76 ,  H01L21/31

    CPC分类号： H01L21/32139 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/32136 ,  H01L29/4966 ,  Y10S257/90

    摘要： A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.

    摘要翻译： 提供了一种栅极电极结构，其从底部到顶部包括任选的，但优选的金属层，富含Ge的层和富含Si的层。 富含Ge的层的侧壁包括表面钝化层。 本发明的栅极电极结构用作MOSFET的低温电激活栅电极，其中其材料及其制造方法与现有的MOSFET制造技术相兼容。 本发明的栅电极结构在低处理温度（小于750℃的数量级）下被电激活。 此外，本发明的栅电极结构还使栅极耗尽效应最小化，不会污染标准MOS制造设备，并且具有足够低的暴露表面的反应性，使得这种栅电极结构与常规MOSFET处理步骤相容。

    STRUCTURE AND METHOD TO FORM SEMICONDUCTOR-ON-PORES (SOP) FOR HIGH DEVICE PERFORMANCE AND LOW MANUFACTURING COST
    83.
    发明申请
    STRUCTURE AND METHOD TO FORM SEMICONDUCTOR-ON-PORES (SOP) FOR HIGH DEVICE PERFORMANCE AND LOW MANUFACTURING COST 有权
    用于形成用于高器件性能和低制造成本的半导体器件（SOP）的结构和方法

    公开(公告)号：US20080179712A1

    公开(公告)日：2008-07-31

    申请号：US12062164

    申请日：2008-04-03

    申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

    发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

    IPC分类号： H01L29/06 ,  H01L21/76

    CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

    摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

    摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

    SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
    87.
    发明授权
    SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth 有权
    SiGe晶格工程使用氧化，稀化和外延再生长的组合

    公开(公告)号：US07026249B2

    公开(公告)日：2006-04-11

    申请号：US10448954

    申请日：2003-05-30

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： H01L21/302

    CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

    摘要： The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

    摘要翻译： 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

    Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
    88.
    发明授权
    Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 失效
    通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体

    公开(公告)号：US06991998B2

    公开(公告)日：2006-01-31

    申请号：US10883883

    申请日：2004-07-02

    申请人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

    IPC分类号： H01L21/20

    CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

    摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

    摘要翻译： 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。