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    Ground via clustering for crosstalk mitigation
    82.
    发明授权
    Ground via clustering for crosstalk mitigation 有权

    公开(公告)号：US09230900B1

    公开(公告)日：2016-01-05

    申请号：US14575956

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/52 ,  H01L23/498

    CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    Interconnect loss of high density package with magnetic material
    84.
    发明授权
    Interconnect loss of high density package with magnetic material 有权

    公开(公告)号：US12009320B2

    公开(公告)日：2024-06-11

    申请号：US16596383

    申请日：2019-10-08

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Cemil Geyik ,  Jiwei Sun ,  Gang Duan ,  Kemal Aygün

    IPC: H01L23/49 ,  H01L23/498 ,  H01L23/64

    CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866

    Abstract: Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.

    Dielectric-filled trench isolation of vias
    87.
    发明授权
    Dielectric-filled trench isolation of vias 有权

    公开(公告)号：US11887932B2

    公开(公告)日：2024-01-30

    申请号：US17684163

    申请日：2022-03-01

    Applicant: INTEL CORPORATION

    Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

    IPC: H01L23/538 ,  H01L21/762 ,  H01L25/065 ,  H01L29/06 ,  H01L21/765

    CPC classification number: H01L23/5384 ,  H01L21/765 ,  H01L21/76283 ,  H01L25/0655 ,  H01L29/0649

    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

    Ground via clustering for crosstalk mitigation
    88.
    发明授权
    Ground via clustering for crosstalk mitigation 有权

    公开(公告)号：US11742275B2

    公开(公告)日：2023-08-29

    申请号：US17566523

    申请日：2021-12-30

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    Optimal signal routing performance through dielectric material configuration designs in package substrate
    89.
    发明授权
    Optimal signal routing performance through dielectric material configuration designs in package substrate 有权

    公开(公告)号：US11574862B2

    公开(公告)日：2023-02-07

    申请号：US16392171

    申请日：2019-04-23

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Gang Duan ,  Kemal Aygün ,  Jieying Kong

    IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66

    Abstract: Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

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