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    HYBRID TOPOGRAPHICAL AND CHEMICAL PRE-PATTERNS FOR DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS
    84.
    发明申请
    HYBRID TOPOGRAPHICAL AND CHEMICAL PRE-PATTERNS FOR DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS 有权
    用于方向自组装块状共聚物的混合地理和化学预先图案

    公开(公告)号：US20160244581A1

    公开(公告)日：2016-08-25

    申请号：US14626082

    申请日：2015-02-19

    Applicant: International Business Machines Corporation

    Inventor： Markus Brink ,  Joy Cheng ,  Gregory S. Doerk ,  Alexander M. Friz ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Daniel P. Sanders ,  Gurpreet Singh ,  Melia Tjio ,  HsinYu Tsai

    IPC: C08J7/04 ,  B05D3/04 ,  B05D7/00

    CPC classification number: C08J7/047 ,  B05D1/185 ,  B05D3/0453 ,  B05D5/02 ,  B05D7/53 ,  B05D7/54 ,  C08J2325/14 ,  C08J2333/12 ,  C08J2333/14 ,  C08J2453/00 ,  C23C14/042 ,  C23C14/08 ,  G03F7/0002 ,  H01L21/02118 ,  H01L21/02255 ,  H01L21/0337

    Abstract: Hybrid pre-patterns were prepared for directed self-assembly of a given block copolymer capable of forming a lamellar domain pattern. The hybrid pre-patterns have top surfaces comprising independent elevated surfaces interspersed with adjacent recessed surfaces. The elevated surfaces are neutral wetting to the domains formed by self-assembly. Material below the elevated surfaces has greater etch-resistance than material below the recessed surfaces in a given etch process. Following other dimensional constraints of the hybrid pre-pattern described herein, a layer of the given block copolymer was formed on the hybrid pre-pattern. Self-assembly of the layer produced a lamellar domain pattern comprising self-aligned, unidirectional, perpendicularly oriented lamellae over the elevated surfaces, and parallel and/or perpendicularly oriented lamellae over recessed surfaces. The domain patterns displayed long range order along the major axis of the pre-pattern. The lamellar domain patterns are useful in forming transfer patterns comprising two-dimensional customized features.

    Abstract translation: 制备混合预图案以用于定向自组装能够形成层状结构域图案的给定嵌段共聚物。 混合预图案具有顶表面，其包括散布有相邻凹陷表面的独立升高表面。 升高的表面是通过自组装形成的区域的中性润湿。 在给定的蚀刻工艺中，升高的表面之下的材料比凹陷表面下方的材料具有更大的抗蚀刻性。 按照本文所述的混合预图案的其他尺寸约束，在混合预图案上形成给定嵌段共聚物层。 层的自组装在升高的表面上产生包括自对准的，单向的，垂直取向的薄片的层状结构域图案，以及在凹面上平行和/或垂直取向的薄片。 域模式沿着预图案的长轴显示长距离顺序。 层状结构域图案可用于形成包括二维定制特征的转印图案。

    Tone inverted directed self-assembly (DSA) fin patterning
    85.
    发明授权
    Tone inverted directed self-assembly (DSA) fin patterning 有权
    色调反向定向自组装（DSA）鳍图案

    公开(公告)号：US09368350B1

    公开(公告)日：2016-06-14

    申请号：US14747487

    申请日：2015-06-23

    Applicant: International Business Machines Corporation

    Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

    IPC: H01L21/302 ,  H01L21/033 ,  H01L21/027

    CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

    Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

    Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充翅片图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。

    DSA grapho-epitaxy process with etch stop material
    86.
    发明授权
    DSA grapho-epitaxy process with etch stop material 有权
    具有蚀刻停止材料的DSA图案沉积工艺

    公开(公告)号：US08859433B2

    公开(公告)日：2014-10-14

    申请号：US13793739

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Jassem A. Abdallah ,  Matthew E. Colburn ,  Steven J. Holmes ,  Daiji Kawamura ,  Chi-Chun Liu ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

    IPC: H01L21/00 ,  H01L21/308

    CPC classification number: H01L21/0337 ,  H01L21/0271

    Abstract: A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials.

    Abstract translation: 用于定义用于定向自组装（DSA）材料的模板的方法包括在中性材料上形成蚀刻停止层，在蚀刻停止层上形成掩模层，并在掩模层上形成防反射涂层（ARC）。 使用光刻法在ARC上形成抗蚀剂层以形成模板图案。 ARC和掩模层根据模板图案被反应离子蚀刻到蚀刻停止层以形成模板结构。 从掩模层移除ARC，并修剪模板结构以减小模板结构的宽度。 执行湿蚀刻以去除蚀刻停止层，以允许中性材料形成用于DSA材料的未损坏的DSA模板。

    Structure and method to pattern pitch lines
    87.
    发明授权
    Structure and method to pattern pitch lines 有权

    公开(公告)号：US12148617B2

    公开(公告)日：2024-11-19

    申请号：US17453010

    申请日：2021-11-01

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chanro Park ,  Chi-Chun Liu ,  Stuart Sieg ,  Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen

    IPC: H01L21/033 ,  H01L21/3213

    Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

    BEOL TOP VIA WIRINGS WITH DUAL DAMASCENE VIA AND SUPER VIA REDUNDANCY
    89.
    发明公开
    BEOL TOP VIA WIRINGS WITH DUAL DAMASCENE VIA AND SUPER VIA REDUNDANCY 审中-公开

    公开(公告)号：US20230170293A1

    公开(公告)日：2023-06-01

    申请号：US17536269

    申请日：2021-11-29

    Applicant: International Business Machines Corporation

    Inventor： Yann Mignot ,  Chanro Park ,  Jacques Simon ,  Hsueh-Chung Chen ,  Chi-Chun Liu

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/7684

    Abstract: The present invention relates to integrated circuits and related method steps for forming an IC chip. The method steps result in semiconductor device structures that include redundant same via level formation using a top via subtractive etch and bottom via from dual damascene etch techniques. In embodiments, the same level redundancy via option is optional. Provision of redundant same via level connections using dual damascene processes improves device resistance and capacitive performance. Further method steps result in semiconductor device structures that include a direct super via connection bypassing subtractive etch metal level via formations. These highlighted method steps increase design flexibility—and reduce device footprint (by skipping a metal level) with the benefit of reduced via connection height and shorter metal connections. Such method steps and resulting IC device structures utilizes the underutilized space and allows further size reduction of the IC chips without adversely impacting the device performance.

    Self-aligned top via
    90.
    发明授权
    Self-aligned top via 有权

    公开(公告)号：US11133260B2

    公开(公告)日：2021-09-28

    申请号：US16685192

    申请日：2019-11-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

    IPC: H01L21/302 ,  H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L21/033 ,  H01L21/3213

    Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

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