公开(公告)号：US10083751B1

公开(公告)日：2018-09-25

申请号：US15664014

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US09778875B2

公开(公告)日：2017-10-03

申请号：US14954507

申请日：2015-11-30

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described.

公开(公告)号：US09384785B2

公开(公告)日：2016-07-05

申请号：US14094454

申请日：2013-12-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Emanuele Confalonieri

IPC: G11C8/00 ,  G11C5/14 ,  G11C13/00 ,  G11C16/04

CPC classification number: G11C5/14 ,  G11C13/0004 ,  G11C16/04

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

公开(公告)号：US09189444B2

公开(公告)日：2015-11-17

申请号：US14455718

申请日：2014-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giulio Albini ,  Emanuele Confalonieri

IPC: G06F12/00 ,  G06F13/42 ,  G06F3/06 ,  G06F13/40 ,  G06F12/14

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/14 ,  G06F13/1668 ,  G06F13/4036 ,  G06F13/4221 ,  G06F2212/1052

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract translation: 本文公开的主题涉及包括存储器和控制器的控制器，诸如控制器，其与共享至少一个存储器块的两个或多个接口之间的操作转换相关联地确定块锁定状态。 该装置可以支持单通道或多通道存储器访问，写保护状态逻辑或各种接口优先级方案。

公开(公告)号：US20250156272A1

公开(公告)日：2025-05-15

申请号：US19021490

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US12164773B2

公开(公告)日：2024-12-10

申请号：US17968049

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Capri ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

公开(公告)号：US12099457B2

公开(公告)日：2024-09-24

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

CPC classification number: G06F13/1694

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

公开(公告)号：US20240028249A1

公开(公告)日：2024-01-25

申请号：US17868286

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.

公开(公告)号：US20240004791A1

公开(公告)日：2024-01-04

申请号：US18202783

申请日：2023-05-26

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Nicola Del Gatto

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1024

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups, and the memory controller comprises respective independent caches corresponding to the plurality of channel groups.

公开(公告)号：US20230229560A1

公开(公告)日：2023-07-20

申请号：US17897037

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G06F11/14 ,  G06F12/06 ,  G06F11/10

CPC classification number: G06F11/1435 ,  G06F12/0646 ,  G06F11/1044 ,  G06F2212/1032 ,  G06F2201/805

Abstract: There are provided methods and systems for correcting an error from a memory. For example, there is provided a system for mitigating an error in a memory. The system can include a memory controller communicatively coupled to a host. The memory controller may be configured to receive information associated with a memory location. The information can indicate the error at the memory location. The controller may be configured to perform, upon receiving the information, certain operations. The operations can include copying data around the memory location, placing the copied data in a reserved area. And the operations can further include outputting, to a central controller, a set of physical addresses associated with the reserved area, wherein the central controller is configured to modify the set of physical address to conduct a data recovery off-line.