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    Dynamic termination edge control
    81.
    发明授权
    Dynamic termination edge control 有权

    公开(公告)号：US10148269B1

    公开(公告)日：2018-12-04

    申请号：US15658276

    申请日：2017-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Myung-Ho Bae

    IPC: H03K19/00 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

    Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

    Half-frequency command path
    83.
    发明授权
    Half-frequency command path 有权

    公开(公告)号：US10063234B1

    公开(公告)日：2018-08-28

    申请号：US15649145

    申请日：2017-07-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder

    IPC: H03K21/00 ,  H03K19/0175 ,  G11C11/4076 ,  H03K3/037

    CPC classification number: H03K19/017509 ,  G11C7/1039 ,  G11C7/109 ,  G11C7/222 ,  G11C11/4076 ,  H03K3/037

    Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

    Methods and apparatuses for command shifter reduction
    84.
    发明授权
    Methods and apparatuses for command shifter reduction 有权

    公开(公告)号：US09892770B2

    公开(公告)日：2018-02-13

    申请号：US14693769

    申请日：2015-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Kallol Mazumder

    IPC: G11C7/10 ,  G11C7/22 ,  G06F9/30

    CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

    Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

    Apparatuses with an embedded combination logic circuit for high speed operations
    86.
    发明授权
    Apparatuses with an embedded combination logic circuit for high speed operations 有权

    公开(公告)号：US09762247B1

    公开(公告)日：2017-09-12

    申请号：US15184077

    申请日：2016-06-16

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder

    IPC: G06F7/50 ,  H03K21/40 ,  H03K19/21 ,  H03K21/10 ,  G11C7/10

    CPC classification number: H03K21/40 ,  G06F5/06 ,  G11C7/1087 ,  G11C7/109 ,  G11C8/06 ,  H03K19/21 ,  H03K21/10

    Abstract: Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

    Apparatuses and methods for providing active and inactive clock signals to a command path circuit
    88.
    发明授权
    Apparatuses and methods for providing active and inactive clock signals to a command path circuit 有权
    用于向命令路径电路提供有源和非活动时钟信号的装置和方法

    公开(公告)号：US09424899B2

    公开(公告)日：2016-08-23

    申请号：US14022102

    申请日：2013-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder

    IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C8/10 ,  G11C2207/2272

    Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

    Abstract translation: 描述了用于向命令路径电路提供有源和非活动时钟信号的装置和方法。 一个示例性方法包括向命令路径提供活动时钟信号用于命令循环的第一部分用于背靠背命令的命令。 命令路径对命令进行解码，并响应于时钟信号提供输出命令信号。 该方法还包括向命令路径提供用于命令循环命令的命令循环的第二部分的非活动时钟信号。

    Methods, apparatuses, and circuits for bimodal disable circuits
    90.
    发明授权
    Methods, apparatuses, and circuits for bimodal disable circuits 有权
    双模禁用电路的方法，装置和电路

    公开(公告)号：US08692603B2

    公开(公告)日：2014-04-08

    申请号：US13975100

    申请日：2013-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Eric Booth ,  Tyler J. Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

    IPC: H03K3/00

    CPC classification number: H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

    Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

    Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用

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