公开(公告)号：US08762703B2

公开(公告)日：2014-06-24

申请号：US13868646

申请日：2013-04-23

Applicant: Micron Technology, Inc.

Inventor： Neal A. Galbo ,  Victor Y. Tsai ,  William H. Radke ,  Krishnam R. Dalta

IPC: G06F9/00 ,  G06F9/24 ,  G06F13/00

CPC classification number: G06F9/5077 ,  G06F3/062 ,  G06F3/0644 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0246 ,  G06F2212/7206

Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

Abstract translation: 本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。 一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。 顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。

公开(公告)号：US20140164867A1

公开(公告)日：2014-06-12

申请号：US13746768

申请日：2013-01-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mustafa N. Kaynak ,  William H. Radke ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G06F11/10

CPC classification number: H03M13/3753 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3707

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Abstract translation: 本公开包括与停止用于分层迭代纠错的标准相关的装置和方法。 多种方法可以包括用纠错电路接收码字，用错误校正电路迭代地纠错码字，包括逐层地对码字进行奇偶校验，并在每层之后更新码字。 方法可以包括响应于针对特定层正确的奇偶校验来停止迭代纠错。

公开(公告)号：US20140059251A1

公开(公告)日：2014-02-27

申请号：US14029422

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F13/16

CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1684 ,  G06F13/4282 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract translation: 本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。 许多实施例包括以链式配置耦合到主机的主机和多个设备。 链接配置包括至少一个不直接耦合到主机的设备。 不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。

公开(公告)号：US20130286736A1

公开(公告)日：2013-10-31

申请号：US13903250

申请日：2013-05-28

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

公开(公告)号：US20130250707A1

公开(公告)日：2013-09-26

申请号：US13894543

申请日：2013-05-15

Applicant: Micron Technology, Inc.

Inventor： Sarin Vishal ,  Dzung H. Nguyen ,  William H. Radke

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.

Abstract translation: 装置具有控制器。 控制器被配置为代替存储器块序列的缺陷存储器块来寻址一系列存储器块的无缺陷存储器块，使得非缺陷存储器块替换有缺陷的存储器块。 无缺陷存储器块是跟随可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的邻近的无缺陷存储器块。 所述控制器被配置为基于所述无缺陷存储器块的实际位置对所述缺陷存储器块进行替换的所述非缺陷存储器块施加电压延迟校正。

公开(公告)号：US20130080864A1

公开(公告)日：2013-03-28

申请号：US13680908

申请日：2012-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke

IPC: H03M13/23

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/005 ,  H03M13/235 ,  H03M13/2933 ,  H03M13/353 ,  H03M13/6362 ,  H03M13/6375

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

公开(公告)号：US10193577B2

公开(公告)日：2019-01-29

申请号：US14811339

申请日：2015-07-28

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  William H. Radke ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  H03M13/29 ,  H03M13/15

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

公开(公告)号：US10089250B2

公开(公告)日：2018-10-02

申请号：US14992612

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/42 ,  G06F13/10 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

公开(公告)号：US09779828B2

公开(公告)日：2017-10-03

申请号：US15091078

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/34 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3418

Abstract: Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

公开(公告)号：US20160203875A1

公开(公告)日：2016-07-14

申请号：US15075768

申请日：2016-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

Abstract translation: 存储器件具有控制器。 控制器被配置为使得存储器件禁止对一组存储器单元进行编程。 控制器被配置为使存储器件施加编程脉冲来控制该组存储器单元的栅极。 控制器被配置为确定响应于编程脉冲的存储器单元组经历的干扰量。 控制器被配置为响应于干扰量来确定程序窗口。