公开(公告)号：US20090231913A1

公开(公告)日：2009-09-17

申请号：US12090375

申请日：2005-10-17

申请人： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

发明人： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： There is provided a technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

摘要翻译： 提供了一种能够提高设定操作的速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

公开(公告)号：US07414283B2

公开(公告)日：2008-08-19

申请号：US11415129

申请日：2006-05-02

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07304345B2

公开(公告)日：2007-12-04

申请号：US11266430

申请日：2005-11-04

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US20070040208A1

公开(公告)日：2007-02-22

申请号：US11589095

申请日：2006-10-30

申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： H01L29/76

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20070029676A1

公开(公告)日：2007-02-08

申请号：US11489668

申请日：2006-07-20

申请人： Norikatsu Takaura ,  Nozomu Matsuzaki

发明人： Norikatsu Takaura ,  Nozomu Matsuzaki

IPC分类号： H01L23/52

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.

摘要翻译： 在半导体衬底上形成由防腐蚀膜，由硫族化物制成的记录层和上电极膜形成的电阻元件，形成第一和第二绝缘膜以覆盖电阻元件，用于暴露的通孔 上电极膜通过第一和第二绝缘膜形成，并且在通孔中形成用于与上电极膜电连接的插头。 为了形成通孔，将由氮化硅制成的第一绝缘膜用作蚀刻停止件，以在第二绝缘膜上进行干蚀刻。 然后，对第一绝缘膜进行干法蚀刻，以使上电极膜从通孔露出。

公开(公告)号：US07141475B2

公开(公告)日：2006-11-28

申请号：US10954102

申请日：2004-09-30

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US07132718B2

公开(公告)日：2006-11-07

申请号：US10726507

申请日：2003-12-04

申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20060113520A1

公开(公告)日：2006-06-01

申请号：US11289410

申请日：2005-11-30

申请人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

发明人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

IPC分类号： H01L29/04

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

摘要： Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of the device is high since a large current requires to rewrite memory information due to low resistance. A portion of constituent elements for a chalcogenide comprises nitride, oxide or carbide which are formed to the boundary between the chalcogenide film and a metal plug as an underlying electrode and to the grain boundary of chalcogenide crystals thereby increasing the phase change temperature and high Joule heat can be generated even by a small current by increasing the resistance of the film.

摘要翻译： 这里公开了一种使用硫族化物膜的相变存储器半导体集成电路器件，其解决了由于相变温度低导致能够确保长时间存储保持的操作温度低的问题，并且同时存在功率 器件的消耗很高，因为大电流需要由于低电阻而重写存储器信息。 硫族化物的一部分组成元素包括氮化物，氧化物或碳化物，其形成于作为下伏电极的硫族化物膜和金属栓之间的边界以及硫族化物晶体的晶界上，从而增加相变温度和高焦耳热 即使通过增加膜的电阻也能通过小的电流产生。

公开(公告)号：US20050237805A1

公开(公告)日：2005-10-27

申请号：US11156538

申请日：2005-06-21

申请人： Nozomu Matsuzaki ,  Hideaki Kurata ,  Takayuki Kawahara

发明人： Nozomu Matsuzaki ,  Hideaki Kurata ,  Takayuki Kawahara

IPC分类号： G11C7/06 ,  G11C7/18 ,  G11C11/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  H01L27/02 ,  H01L27/105

CPC分类号： G11C16/24 ,  G11C7/065 ,  G11C7/067 ,  G11C7/18 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526

摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.

摘要翻译： 本发明的半导体非易失性存储装置，其使存储器单元直接驱动到本地位线，其中本地位线的输出由单独提供的信号放大晶体管的栅电极接收，并且 信号放大晶体管用于驱动具有大负载能力的全局位线。 由于具有高于存储单元的驱动功率的放大晶体管驱动全局位线的寄生电容，因此可以高速读出存储在存储单元中的信息。 因此，存储装置用于存储用于控制微型计算机等的程序代码，从而提高系统性能。

公开(公告)号：US06944056B2

公开(公告)日：2005-09-13

申请号：US10473817

申请日：2001-04-02

申请人： Nozomu Matsuzaki ,  Hideaki Kurata ,  Takayuki Kawahara

发明人： Nozomu Matsuzaki ,  Hideaki Kurata ,  Takayuki Kawahara

IPC分类号： G11C7/06 ,  G11C7/18 ,  G11C11/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  H01L27/02 ,  H01L27/105 ,  G11C11/401

CPC分类号： G11C16/24 ,  G11C7/065 ,  G11C7/067 ,  G11C7/18 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526

摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.