1-Alpha-Halo-2,2-Difluoro-2-Deoxy-D-Ribofuranose Derivatives and Process for the Preparation Thereof
    81.
    发明申请
    1-Alpha-Halo-2,2-Difluoro-2-Deoxy-D-Ribofuranose Derivatives and Process for the Preparation Thereof 失效
    1-α-卤代-2,2-二氟-2-脱氧-D-呋喃核糖衍生物及其制备方法

    公开(公告)号:US20070238865A1

    公开(公告)日:2007-10-11

    申请号:US11572790

    申请日:2005-06-21

    IPC分类号: C07H15/00

    CPC分类号: C07H3/08

    摘要: 1-α-halo-2,2-difluoro-2-deoxy-D-ribofuranose derivative of formula (I) having the 3-hydroxy group protected with a biphenylcarbonyl group is a solid which can be easily purified by a simple procedure such as recrystallization, and therefore, it can be advantageously used as an intermediate in the preparation of gemcitabine in a large scale. Further, the 1-α-halo-2,2-difluoro-2-deoxy-D-ribofuranose derivative of formula (I) can be prepared with high stereoselectivity using the compound of formula (V) as an intermediate.

    摘要翻译: 具有用联苯基羰基保护的3-羟基的式(I)的1-α-卤代-2,2-二氟-2-脱氧-D-呋喃核糖衍生物是可以通过简单的方法容易地纯化的固体,例如 重结晶,因此可以有利地用作大量制备吉西他滨的中间体。 此外,式(I)的1-α-卤代-2,2-二氟-2-脱氧-D-呋喃核糖衍生物可以使用式(V)化合物作为中间体以高立体选择性制备。

    Fabricating method of printed circuit board having embedded component
    82.
    发明申请
    Fabricating method of printed circuit board having embedded component 审中-公开
    具有嵌入式元件的印刷电路板的制造方法

    公开(公告)号:US20070111380A1

    公开(公告)日:2007-05-17

    申请号:US11598141

    申请日:2006-11-13

    IPC分类号: H01L21/00

    摘要: A method of fabricating a printed circuit board having embedded components is disclosed. The method of fabricating a printed circuit board having embedded components according to an embodiment of the present invention comprises stacking a first conductive layer and a second conductive layer on a substrate in order, forming a hole in the second conductive layer and filling with dielectric material, stacking a third conductive layer on the second conductive layer and removing portions to form an upper electrode located on the dielectric material and a pad electrically connected with the first conductive layer, and stacking an insulation layer on the third conductive layer and forming a via hole and an outer layer circuit electrically connected with the upper electrode and the pad, so that it is easy to process the dielectric material to have a uniform thickness, and the capacitor and the resistor can be implemented simultaneously.

    摘要翻译: 公开了一种制造具有嵌入式部件的印刷电路板的方法。 根据本发明的实施例的制造具有嵌入部件的印刷电路板的方法包括在基板上层叠第一导电层和第二导电层,以在第二导电层中形成孔并填充电介质材料, 在所述第二导电层上堆叠第三导电层并去除部分以形成位于所述电介质材料上的上电极和与所述第一导电层电连接的焊盘,以及在所述第三导电层上堆叠绝缘层并形成通孔,以及 与上电极和焊盘电连接的外层电路,使得容易将电介质材料加工成具有均匀的厚度,并且可以同时实现电容器和电阻器。

    Organic light emitting display and a deposition method
    83.
    发明申请
    Organic light emitting display and a deposition method 审中-公开
    有机发光显示器和沉积方法

    公开(公告)号:US20070057625A1

    公开(公告)日:2007-03-15

    申请号:US11501602

    申请日:2006-08-08

    IPC分类号: H01L51/52 H01L51/56 C23C14/34

    摘要: Disclosed are an organic light emitting display and a deposition method for depositing an electrode or a passivation layer by means of a box cathode sputtering method or a facing target sputtering method by mixing Ar with an inert gas heavier than Ar gas. The present embodiments provide an organic light emitting display including a substrate; a thin film transistor formed on the substrate; a first electrode formed on the thin film transistor; an organic layer formed on the first electrode; and a second electrode layer sputter-deposited on the organic layer by mixing Ar gas with an inert gas heavier than said Ar using a box cathode sputtering method or a facing target sputtering method.

    摘要翻译: 公开了通过将Ar与比Ar气体重的惰性气体混合的方式,通过箱式阴极溅射法或面对靶溅射法沉积电极或钝化层的有机发光显示器和沉积方法。 本实施例提供一种包括基板的有机发光显示器; 形成在所述基板上的薄膜晶体管; 形成在薄膜晶体管上的第一电极; 形成在所述第一电极上的有机层; 以及通过使用箱式阴极溅射法或面对靶溅射法将Ar气体与比所述Ar重的惰性气体混合在有机层上溅射沉积的第二电极层。

    Phytase produced from citrobacter braakii
    85.
    发明申请
    Phytase produced from citrobacter braakii 有权
    由柠檬酸杆菌产生的植酸酶

    公开(公告)号:US20060194298A1

    公开(公告)日:2006-08-31

    申请号:US10550758

    申请日:2004-03-25

    IPC分类号: C12N9/00

    CPC分类号: C12N9/16 A23K20/189

    摘要: The present invention relates to novel phytase enzyme, a gene coding the enzyme, and a Citrobacter sp. producing the enzyme. Particularly, the present invention relates to the phytase enzyme produced from Citrobacter sp. having (a) molecular weight of 47 kDa, (b) optimal pH of 3.5-4.5, (c) optimal temperature of 45-55° C., (d) as substrates phytate, p-nitrophenyl phosphate, tetrasodium pyrophosphate, ATP or ADP, (e) Michaelis constant of 0.3-0.5 mM utilizing phytate as substrate, and (f) high resistance to protease such as pepsin, trypsin, papain, elastase or pancreatin. The present invention also relates to the gene coding the phytase enzyme and the Citrobacter braakii producing the enzyme. The phytase enzyme and the Citrobacter braakii producing the enzyme of the present invention can be used in manufacturing a feed of monogastrics as feed additive and in recovering a specific decomposition product of phytate at low price.

    摘要翻译: 本发明涉及新型植酸酶,编码酶的基因和柠檬酸杆菌属。 产生酶。 特别地,本发明涉及由柠檬酸杆菌属(Citrobacter sp。)生产的植酸酶。 (a)分子量为47kDa,(b)最佳pH为3.5-4.5,(c)最适温度为45-55℃,(d)为底物植酸盐,磷酸对硝基苯酯,焦磷酸四钠,ATP或 ADP,(e)利用植酸盐作为底物的0.3-0.5mM的米氏常数,和(f)对蛋白酶如胃蛋白酶,胰蛋白酶,木瓜蛋白酶,弹性蛋白酶或胰酶的高抗性。 本发明还涉及编码植酸酶的基因和产生该酶的柠檬酸杆菌(Citrobacter braakii)。 产生本发明酶的植酸酶和柠檬酸杆菌可用于制造作为饲料添加剂的单胃饲料的饲料,并以低价回收植酸盐的特定分解产物。

    Memory test circuit and test system
    89.
    发明申请
    Memory test circuit and test system 失效
    内存测试电路和测试系统

    公开(公告)号:US20050117420A1

    公开(公告)日:2005-06-02

    申请号:US10994140

    申请日:2004-11-19

    CPC分类号: G11C29/14 G11C2029/0405

    摘要: A memory test circuit and a test system are provided. The memory test circuit comprises a memory which outputs stored data through n-bit data output pins, and a built-in self test (BIST) unit. The BIST unit writes test data in the memory, and by comparing the test data output from the memory with expected data, determines a failure cell address in the memory. The BIST unit generates k preliminary failure signals having failure information indicating whether the test data correspond with the expected data, and outputs the k preliminary failure signals for m cycles of a clock signal, by outputting k/m preliminary failure signals each cycle as first through k/m failure signals. When a test operation is performed, the memory divides the n-bit data output pins into eight groups to make the groups correspond to respective areas in the memory, and when a repair operation is performed, repair is performed in each area of the memory corresponding to the eight groups of the data output pins. In the memory test circuit and test system, the BIST unit testing a memory and generating a failure signal is disposed in a memory apparatus and a failure analysis circuit analyzing a failure signal output by the BIST unit is disposed in the test apparatus. Thus, the burden of designing a memory for test operation can be reduced. In addition, by outputting failure signals after dividing the signals, the overhead of pins of the test apparatus can be reduced.

    摘要翻译: 提供记忆测试电路和测试系统。 存储器测试电路包括通过n位数据输出引脚输出存储的数据的存储器和内置的自检(BIST)单元。 BIST单元将测试数据写入存储器,并通过将存储器输出的测试数据与预期数据进行比较,确定存储器中的故障单元地址。 BIST单元生成具有指示测试数据是否与期望数据相对应的故障信息的k个初始故障信号,并且通过每个周期作为第一到第一通过输出k / m个初步故障信号来输出用于时钟信号的m个周期的k个初步故障信号 k / m故障信号。 当执行测试操作时,存储器将n位数据输出引脚分成八组,使组对应于存储器中的相应区域,当执行修复操作时,在存储器对应的每个区域中执行修复 到八组数据输出引脚。 在存储器测试电路和测试系统中,测试存储器并产生故障信号的BIST单元被布置在存储器装置中,并且分析由BIST单元输出的故障信号的故障分析电路设置在测试装置中。 因此,可以减少设计用于测试操作的存储器的负担。 此外,通过在分割信号之后输出故障信号,可以减少测试装置的引脚的开销。

    Method of fabricating cavity capacitor embedded in printed circuit board
    90.
    发明授权
    Method of fabricating cavity capacitor embedded in printed circuit board 有权
    埋入印刷电路板的空腔电容器的制造方法

    公开(公告)号:US08966746B2

    公开(公告)日:2015-03-03

    申请号:US13064847

    申请日:2011-04-20

    摘要: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.

    摘要翻译: 一种嵌入在印刷电路板中的空腔电容器的方法,包括分别用作功率层和接地层的两个导电层和放置在两个导电层之间的第一介电层,所述方法包括: 上导电层和除了两个导电层的下导电层之外的第一电介质层,以允许在两个导电层之间形成腔,下导电层假定用作空腔电容器的任一电极; 在所述空腔上堆叠电介质材料以允许在所述空腔中形成具有比所述第一电介质层更低的台阶部分的第二电介质层; 并且在第二电介质层的上部和空腔的侧部上堆叠导电材料,以允许上部导电层用作空腔电容器的另一个电极。