公开(公告)号：US20150130021A1

公开(公告)日：2015-05-14

申请号：US14079488

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/0053

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract translation: 一些实施方式提供了一种集成器件（例如，半导体器件），其包括衬底中的衬底和电感器。 在一些实施方案中，电感器是螺线管电感器。 电感器包括一组绕组。 该组绕组具有内周。 该组绕组包括一组互连和一组通孔。 该组互连和一组通孔位于该组绕组的内周边之外。 在一些实施方案中，该组绕组还包括一组捕获垫。 该组互连通过一组捕获垫耦合到该组通孔。 在一些实施方式中，该组绕组具有外周边。 该组焊盘耦合到该组互连件，使得该组焊盘至少部分地位于该组绕组的外周边之外。

公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC: H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract translation: 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。

公开(公告)号：US20240421790A1

公开(公告)日：2024-12-19

申请号：US18336305

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H03H3/08 ,  H03H9/02 ,  H03H9/64

Abstract: A package includes a device that includes electrodes disposed on a piezoelectric layer on a first, front side of a first substrate and vertical interconnect accesses (vias) that extend through the substrate to couple the electrodes to a second, back side of the first substrate. The vias may be through-substrate vias (TSVs). Employing a first substrate (e.g., silicon) in which vias can be formed, the electrodes on the front side can be coupled to interconnects on the back side to minimize electrical path distances to and from the device for a higher a Q factor. Also, a capacitor may be formed on a second, back side of the substrate and coupled to an electrode of the device by a via rather than having an electrical path from a first substrate, to an external capacitor on a package substrate. A thermal conductive path is also reduced for improved heat dissipation.

公开(公告)号：US11894366B2

公开(公告)日：2024-02-06

申请号：US18298211

申请日：2023-04-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H01L27/08 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L27/0805 ,  H01L23/642 ,  H01L25/0657 ,  H01L25/105 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181 ,  H01L29/945 ,  H10B12/038 ,  H10B12/37 ,  H10B12/39 ,  H01L2924/19041

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

公开(公告)号：US11830819B2

公开(公告)日：2023-11-28

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy ,  Stanley Seungchul Song ,  Jonghae Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US11791226B2

公开(公告)日：2023-10-17

申请号：US17017407

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Ranadeep Dutta ,  Jonghae Kim

IPC: H01L23/15 ,  H01L21/768 ,  H01L21/321 ,  H01L21/48 ,  H01L23/522 ,  H01L23/373 ,  C04B35/111 ,  C04B37/02 ,  H03H9/10 ,  H03H3/10 ,  H01L27/06 ,  H03H3/02

CPC classification number: H01L23/15 ,  C04B35/111 ,  C04B37/025 ,  H01L21/3212 ,  H01L21/4807 ,  H01L21/76801 ,  H01L23/3738 ,  H01L23/5222 ,  H01L27/0629 ,  H03H3/10 ,  H03H9/1014 ,  C04B2235/963 ,  H03H2003/027

Abstract: Disclosed are devices and methods for semiconductor devices including a ceramic substrate. Aspects disclosed include semiconductor device including an electrical component, an alumina ceramic substrate and a substrate-film. The substrate-film is deposited on the alumina ceramic substrate. The substrate-film has a planar substrate-film surface opposite the alumina ceramic substrate. The electrical component is formed on the substrate-film surface of the substrate-film on the alumina ceramic substrate.

公开(公告)号：US11652468B2

公开(公告)日：2023-05-16

申请号：US16922471

申请日：2020-07-07

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim

IPC: H03H9/46 ,  H03H9/02

CPC classification number: H03H9/46 ,  H03H2009/02165 ,  H03H2009/02322

Abstract: Disclosed is a gallium arsenide (GaAs) enabled tunable filter for, e.g., 6 GHz Wi-Fi RF Frontend, with integrated high-performance varactors, metal-insulator-metal (MIM) capacitors, and 3D solenoid inductors. The tunable filter comprises a hyper-abrupt variable capacitor (varactor) high capacitance tuning ratio. The tunable filter also comprises a GaAs substrate in which through-GaAs-vias (TGV) are formed. The varactor along with the MIM capacitors and the 3D inductors is formed in an upper conductive structure on upper surface of the GaAs substrate. Lower conductive structure comprising lower conductors is formed on lower surface of the GaAs substrate. Electrical coupling between the lower and upper conductive structures is provided by the TGVs. The tunable filter can be integrated with radio frequency front end (RFFE) devices.

公开(公告)号：US11652101B2

公开(公告)日：2023-05-16

申请号：US17144411

申请日：2021-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H01L27/08 ,  H01L25/10 ,  H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

CPC classification number: H01L27/0805 ,  H01L25/105 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181 ,  H01L29/945

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220231660A1

公开(公告)日：2022-07-21

申请号：US17153520

申请日：2021-01-20

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H03H9/02 ,  H03H9/145 ,  H03H3/08

Abstract: A surface acoustic wave (SAW) device includes a first interdigital transducer (IDT) and a second IDT each including interdigital electrodes disposed on a first surface of a substrate of piezoelectric material. The SAW device includes a diamond bridge enclosing an air cavity over a wave propagation region on the first surface of the substrate. The diamond bridge has a reduced height and provides improved thermal conductivity to avoid a reduction in performance and/or life span caused by heat generated in the SAW device. A process of fabricating a SAW device includes forming the first IDT and the second IDT in a metal layer on a first surface of a substrate comprising a piezoelectric material, the first IDT and the second IDT disposed in a wave propagation region of the first surface of the substrate, and forming a diamond bridge disposed above the wave propagation region.