公开(公告)号：US20200161278A1

公开(公告)日：2020-05-21

申请号：US16598806

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA

IPC: H01L25/065 ,  H01L25/00 ,  H03K17/687

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

公开(公告)号：US20190393148A1

公开(公告)日：2019-12-26

申请号：US16438018

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8238

Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.

公开(公告)号：US20190187370A1

公开(公告)日：2019-06-20

申请号：US16176327

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Shinichi WATANUKI

IPC: G02B6/122

CPC classification number: G02B6/122 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12142

Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.

公开(公告)号：US20190072717A1

公开(公告)日：2019-03-07

申请号：US16036455

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  G02B6/125

CPC classification number: G02B6/1228 ,  G02B6/125 ,  G02B2006/12061 ,  G02B2006/12119

Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.

公开(公告)号：US20190004342A1

公开(公告)日：2019-01-03

申请号：US15976912

申请日：2018-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Shinichi KUWABARA

IPC: G02F1/01 ,  G02F1/025

Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.

公开(公告)号：US20180366409A1

公开(公告)日：2018-12-20

申请号：US15954213

申请日：2018-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/64 ,  H01L23/552 ,  H01L21/8238 ,  H01L25/00

CPC classification number: H01L23/5227 ,  H01L21/26513 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/552 ,  H01L23/645 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06562 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

公开(公告)号：US20180108609A1

公开(公告)日：2018-04-19

申请号：US15843896

申请日：2017-12-15

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu NEMOTO ,  Yasutaka NAKASHIBA ,  Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Kazunori GO ,  Hiroshi OE ,  Noriko YOSHIKAWA

IPC: H01L23/522 ,  G01R33/06 ,  G01R31/26 ,  H01L49/02 ,  H01F27/28 ,  H01L23/528

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01F2017/0073 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

公开(公告)号：US20180052338A1

公开(公告)日：2018-02-22

申请号：US15798780

申请日：2017-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki KUNISHIMA ,  Yasutaka NAKASHIBA ,  Masaru WAKABAYASHI ,  Shinichi WATANUKI

IPC: G02F1/025 ,  G02B6/132 ,  H01L23/532 ,  G02B6/125 ,  G02B6/28 ,  G02B6/12

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

公开(公告)号：US20180047667A1

公开(公告)日：2018-02-15

申请号：US15619703

申请日：2017-06-12

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L23/5226 ,  H01L28/10

Abstract: A semiconductor device is provided with a SOI substrate including a semiconductor substrate, a BOX layer on the semiconductor substrate, and a semiconductor layer on the BOX layer, a multilayer wiring formed over a main surface of the SOI substrate, and an inductor comprised of the multilayer wiring. In a region located below the inductor, the BOX layer and the semiconductor layer are separated into a plurality of regions by an element isolation portion, and a dummy gate electrode is formed on a part of the semiconductor layer, which is located in each of the plurality of regions, via a dummy gate insulating film.

公开(公告)号：US20170315312A1

公开(公告)日：2017-11-02

申请号：US15648214

申请日：2017-07-12

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/12

CPC classification number: G02B6/428 ,  G02B6/43 ,  G02B2006/12061

Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.