公开(公告)号：US20050158986A1

公开(公告)日：2005-07-21

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC分类号： C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC分类号： H01L21/28518 ,  C23C14/16

摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

摘要翻译： 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US20050054202A1

公开(公告)日：2005-03-10

申请号：US10655972

申请日：2003-09-04

申请人： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

发明人： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC分类号： H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

摘要： A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

摘要翻译： 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US20050045092A1

公开(公告)日：2005-03-03

申请号：US10653852

申请日：2003-09-03

申请人： Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

IPC分类号： C30B25/02 ,  C30B25/14 ,  H01L21/314 ,  H01L21/316 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/0228 ,  C30B25/02 ,  C30B25/14 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645

摘要： An ALD method is described for depositing a composite layer comprised of three to five elements including one or two metals, Si, B and N. A metal containing gas is injected into a process chamber and purged followed by a N source gas and a purge and/or a Si or B source gas and a purge to complete a cycle and form a monolayer. A predetermined number of monolayers each having two or three elements is deposited to provide a composite film with good step coverage and a well controlled composition. The resulting layer is especially useful as a diffusion barrier layer for copper. Alternatively, a three component layer comprised of Hf, Zr, and O may be deposited and serves as a gate dielectric layer in a MOSFET device. The invention is also a thin film comprised of a plurality of monolayers each having two or three elements.

摘要翻译： 描述了一种ALD方法，用于沉积由包括一种或两种金属Si，B和N的三至五个元素组成的复合层。将含金属的气体注入到处理室中，然后吹扫N源气体和吹扫， /或Si或B源气体和吹扫以完成循环并形成单层。 沉积预定数量的具有两个或三个元素的单层，以提供具有良好的步骤覆盖率和良好控制的组合物的复合膜。 所得的层特别适用于铜的扩散阻挡层。 或者，可以沉积由Hf，Zr和O组成的三组分层，并且用作MOSFET器件中的栅介质层。 本发明也是由多个单层组成的薄膜，每个单层具有两个或三个元素。

公开(公告)号：US06686280B1

公开(公告)日：2004-02-03

申请号：US09989802

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

公开(公告)号：US06531389B1

公开(公告)日：2003-03-11

申请号：US09467130

申请日：1999-12-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang

发明人： Shau-Lin Shue ,  Mei-Yun Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  Y10S438/958

摘要： A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer. Incident to employing the purging of the via to form the purged via and the plasma passivating of the purged via to form the plasma passivated purged via, the conductor stud layer when formed into the plasma passivated purged via is formed with attenuated contact resistance with respect to the plasma passivated patterned conductor layer.

摘要翻译： 一种通过电介质层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的导体层。 然后形成覆盖图案化导体层的电介质层。 然后通过电介质层形成通孔以访问图案化的导体层，其中通孔不完全地着落在图案化的导体层上。 然后在使用真空吹扫方法的同时吹扫通孔以形成清洗的通孔。 然后钝化净化的通孔并钝化暴露在清洗过的通孔内的图案化导体层，同时采用等离子体钝化方法形成等离子体钝化清洗的通孔和等离子体钝化的图案化导体层。 最后，然后形成通过导体柱层被钝化的等离子体钝化。 为了采用清洗通孔以形成清洗过的通孔和被清除通孔的等离子体钝化以形成等离子体钝化净化通孔的事件，当形成等离子体钝化净化过的通孔时，导体柱层形成相对于 等离子体钝化图案化导体层。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

公开(公告)号：US06245675B1

公开(公告)日：2001-06-12

申请号：US09489966

申请日：2000-01-24

申请人： Mong-Song Liang ,  Shau-Lin Shue

发明人： Mong-Song Liang ,  Shau-Lin Shue

IPC分类号： H01L214763

CPC分类号： H01L21/76879

摘要： A new method of metallization using a three-dimensional aluminum reservoir to increase the electromigration lifetime of a tungsten plug in the fabrication of integrated circuits is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. Aluminum lines are formed over the insulating layer. An intermetal dielectric layer is deposited overlying the aluminum lines. Via openings are made through the intermetal dielectric layer to the aluminum lines. Aluminum is selectively deposited into the via openings to form aluminum reservoirs in the bottom of the via openings wherein the aluminum does not completely fill the via openings. Tungsten plugs are formed within the via openings overlying the aluminum reservoirs wherein the aluminum reservoirs provide a source for electrons to replenish electrons lost through electromigration to complete formation of tungsten plug metallization with increased electromigration lifetime in the fabrication of integrated circuits.

摘要翻译： 实现了在集成电路制造中使用三维铝储存器来增加钨插塞的电迁移寿命的新的金属化方法。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 在绝缘层上形成铝线。 金属间电介质层沉积在铝线上。 通过开口穿过金属间电介质层到铝线。 选择性地将铝沉积到通孔开口中以在通孔开口的底部形成铝储存器，其中铝不完全填充通孔。 钨插塞形成在覆盖铝储存器的通孔开口中，其中铝储存器提供电子源以补充通过电迁移损失的电子，以在集成电路的制造中增加电迁移寿命来完成钨插塞金属化的形成。

公开(公告)号：US06221758B1

公开(公告)日：2001-04-24

申请号：US09225064

申请日：1999-01-04

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

公开(公告)号：US06207568B1

公开(公告)日：2001-03-27

申请号：US09200554

申请日：1998-11-27

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

摘要翻译： 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。