公开(公告)号：US10732945B1

公开(公告)日：2020-08-04

申请号：US16422845

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

公开(公告)号：US20200210191A1

公开(公告)日：2020-07-02

申请号：US16684410

申请日：2019-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, JR. ,  Paul D. Gauvreau

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory, the fetch-packet containing a bitwise distance from an entry point of the first hyper-block to a predicted exit point; executing a first branch instruction of the first hyper-block, wherein the first branch instruction corresponds to a first exit point, and wherein the first branch instruction includes an address corresponding to an entry point of a second hyper-block; storing, responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point; and moving a program counter from the first exit point of the first hyper-block to the entry point of the second hyper-block.

公开(公告)号：US10162641B2

公开(公告)日：2018-12-25

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/10

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20180357448A1

公开(公告)日：2018-12-13

申请号：US16047298

申请日：2018-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

IPC: G06F21/78 ,  G06F12/14 ,  G06F12/1081 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/28 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/42 ,  H04L29/06 ,  G06F21/79

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

公开(公告)号：US09788011B2

公开(公告)日：2017-10-10

申请号：US15403311

申请日：2017-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: G06F9/30 ,  H04N19/43 ,  H04N19/513 ,  H04N19/56 ,  H04N19/433

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

公开(公告)号：US09465741B2

公开(公告)日：2016-10-11

申请号：US14056729

申请日：2013-10-17

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Daniel B Wu ,  Matthew D Pierson ,  Timothy D. Anderson

IPC: G06F13/40 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。

公开(公告)号：US09239735B2

公开(公告)日：2016-01-19

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/45 ,  G06F9/48 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20150026444A1

公开(公告)日：2015-01-22

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20140149690A1

公开(公告)日：2014-05-29

申请号：US14061979

申请日：2013-10-24

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D. Pierson ,  Daniel B. Wu ,  Timothy D. Anderson

IPC: G06F12/08 ,  G06F13/42

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract translation: 本发明结合了多核共享存储器控制器和异步协议转换桥以创建非常有效的异构多处理器系统。 在通过协议转换网桥之后，命令行进通过常规处理器端口。 这允许互连保持不变，同时连接不同处理器的任何组合。 本发明将所有处理器紧密地集成到相同的存储器控​​制器/互连中。

公开(公告)号：US20140115271A1

公开(公告)日：2014-04-24

申请号：US14057205

申请日：2013-10-18

Applicant: Texas Instruments Incorporated

Inventor： Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

IPC: G06F12/08

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this data will be available earlier than if the memory controller stalled this write pending snoop responses. This invention computes write enable strobes for the coherence write data based upon the cache dirty tags. This invention initiates a snoop cycle based upon the address of the coherence write. The stored write enable strobes enable determination of which data to write to the endpoint memory upon a cached and dirty snoop response.

Abstract translation: 本发明加速了对共享存储器的一致性写操作。 本发明立即提交到存储器端点一致写入数据。 因此，如果内存控制器停止了这个写入挂起的侦听响应，那么这个数据将可用。 本发明基于高速缓存脏标签计算用于相干写入数据的写入使能选通。 本发明基于一致性写入的地址启动窥探循环。 存储的写使能选通使得能够确定在高速缓存和脏的窥探响应时哪些数据写入端点存储器。