公开(公告)号：US10157751B1

公开(公告)日：2018-12-18

申请号：US15794262

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao Chang ,  Chao-Hsien Huang ,  Wen-Ting Lan ,  Shi-Ning Ju ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.

公开(公告)号：US20180315602A1

公开(公告)日：2018-11-01

申请号：US15684282

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Li-Te Lin ,  Ru-Gun Liu ,  Min Cao

IPC: H01L21/033

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.

公开(公告)号：US12288722B2

公开(公告)日：2025-04-29

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US12183805B2

公开(公告)日：2024-12-31

申请号：US17333676

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Li-Te Lin ,  Chung-Cheng Wu ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US12094951B1

公开(公告)日：2024-09-17

申请号：US18136493

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US20240282569A1

公开(公告)日：2024-08-22

申请号：US18171508

申请日：2023-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Lo ,  Ding-Kang Shih ,  Tsungyu Hung ,  Chia-Ling Pai ,  Pang-Yen Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/02068 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L23/5226

Abstract: In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

公开(公告)号：US12034059B2

公开(公告)日：2024-07-09

申请号：US18298095

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11942367B2

公开(公告)日：2024-03-26

申请号：US17113836

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan Syun David Yang ,  Li-Te Lin ,  Chun-Jui Huang

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

公开(公告)号：US11843041B2

公开(公告)日：2023-12-12

申请号：US17856892

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L29/517 ,  H01J37/00 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/7848

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

公开(公告)号：US20230386921A1

公开(公告)日：2023-11-30

申请号：US18446728

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan Syun David Yang ,  Li-Te Lin ,  Chun-Jui Huang

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L29/66795 ,  H01L23/535 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/66545 ,  H01L29/165

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.