公开(公告)号：US20200343220A1

公开(公告)日：2020-10-29

申请号：US16928003

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US10727198B2

公开(公告)日：2020-07-28

申请号：US15854704

申请日：2017-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L21/683 ,  H01L25/10 ,  H01L23/29 ,  H01L21/768

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

公开(公告)号：US10515827B2

公开(公告)日：2019-12-24

申请号：US15874541

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/498 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip. The method includes bonding an interposer substrate to the redistribution structure through a conductive structure. The chip is between the interposer substrate and the redistribution structure. The interposer substrate has a recess adjacent to the redistribution structure. A first portion of the chip is in the recess. The interposer substrate includes a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure.

公开(公告)号：US10347574B2

公开(公告)日：2019-07-09

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L23/498 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/373 ,  H01L25/075 ,  H01L23/36 ,  H01L23/367

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US20190139896A1

公开(公告)日：2019-05-09

申请号：US15806342

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure.

公开(公告)号：US10175294B2

公开(公告)日：2019-01-08

申请号：US15481891

申请日：2017-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L23/00 ,  G01R1/04

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US20190006257A1

公开(公告)日：2019-01-03

申请号：US15854720

申请日：2017-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L21/56

Abstract: A semiconductor package including at least one integrated circuit component, a glue material, an insulating encapsulation, and a redistribution circuit structure is provided. The glue material encapsulates the at least one integrated circuit component and has a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface. The insulating encapsulation encapsulates the glue material, wherein an interface is between the glue material and the insulating encapsulation. The redistribution circuit structure is disposed on the at last one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component.

公开(公告)号：US10163816B2

公开(公告)日：2018-12-25

申请号：US15180404

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/10 ,  H01L23/04 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures.

公开(公告)号：US09748156B1

公开(公告)日：2017-08-29

申请号：US15180264

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Shen Yeh ,  Cheng-Lin Huang ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Wen-Yi Lin ,  Ming-Chih Yew ,  Yu-Huan Chen ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/18 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/18 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

公开(公告)号：US12300592B2

公开(公告)日：2025-05-13

申请号：US18351809

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.