公开(公告)号：US06475813B1

公开(公告)日：2002-11-05

申请号：US09929711

申请日：2001-08-13

申请人： Tingkai Li ,  Wei Pan ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Pan ,  Sheng Teng Hsu

IPC分类号： A01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  C30B25/02 ,  C30B29/30 ,  C30B29/32 ,  H01L21/31604

摘要： A method of fabricating a c-axis ferroelectric thin film includes preparing a substrate; depositing a layer of ferroelectric material by metal organic chemical vapor deposition, including using a precursor solution having a ferroelectric material concentration of about 0.1 M/L at a vaporizer temperature of between about 140° C. to 200° C.; and annealing the substrate and the ferroelectric material at a temperature between about 500° C. to 560° C. for between about 30 minutes to 120 minutes.

摘要翻译： 制造c轴铁电薄膜的方法包括：制备基板; 通过金属有机化学气相沉积沉积铁电材料层，包括在蒸发器温度为约140℃至200℃之间使用铁电材料浓度为约0.1M / L的前体溶液; 以及在大约500℃至560℃之间的温度下将所述衬底和所述铁电材料退火约30分钟至120分钟。

公开(公告)号：US06410343B1

公开(公告)日：2002-06-25

申请号：US09301420

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US6048740A

公开(公告)日：2000-04-11

申请号：US187238

申请日：1998-11-05

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。 铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

公开(公告)号：US07514282B2

公开(公告)日：2009-04-07

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒阵列，在二氧化硅棒周围形成Si 3 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4管下面的Si管。 最后，去除Si3N4管。

公开(公告)号：US20080315255A1

公开(公告)日：2008-12-25

申请号：US12199144

申请日：2008-08-27

申请人： Jer-Shen Maa ,  Tingkai Li ,  Douglas J. Tweet ,  Gregory M. Stecker ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Tingkai Li ,  Douglas J. Tweet ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC分类号： H01L29/267

CPC分类号： H01L29/267 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02656 ,  H01L29/045 ,  H01L29/2003

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供具有第一热膨胀系数（TEC）的（111）Si衬底，并且形成覆盖Si衬底的硅 - 锗（SiGe）膜。 沉积SiGe膜上的缓冲层。 缓冲层可以是氮化铝（AlN）或铝 - 氮化镓（AlGaN）。 沉积GaN缓冲层，其具有大于第一TEC的第二TEC。 SiGe电影拥有第三个TEC，其值在第一和第二TEC之间。 一方面，可以形成具有Ge含量比在约0％至50％的范围内的等级SiGe膜，其中Ge含量随着梯度SiGe膜厚度而增加。

公开(公告)号：US07407858B2

公开(公告)日：2008-08-05

申请号：US11403020

申请日：2006-04-11

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/336 ,  H01L31/072

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1641

摘要： A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.

摘要翻译： 制造RRAM的方法包括制备衬底并形成底部电极或衬底。 使用MOCVD或液体MOCVD将PCMO层沉积在底部电极上，随后进行后退火处理。 沉积的PCMO薄膜具有结晶的PCMO结构或纳米尺寸和无定形PCMO结构。 顶部电极形成在PCMO层上。

公开(公告)号：US20080050872A1

公开(公告)日：2008-02-28

申请号：US11510428

申请日：2006-08-24

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/8244 ,  H01L21/8234

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/147

摘要： A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work function of a group of potential cathode materials; and selecting a suitable material for the resistance material from the group of potential resistance materials and selecting a suitable material for the cathode material from the group of potential cathode material, wherein the work function of the cathode material is at least 0.2 eV less than the work function of the resistance material.

摘要翻译： 选择用于RRAM的阴极材料和电阻材料的方法包括确定一组电阻材料的功函数; 确定一组潜在阴极材料的功函数; 并从潜在的电阻材料组中选择合适的电阻材料材料，并从潜在的阴极材料组中选择合适的阴极材料材料，其中阴极材料的功函数比工件小至少0.2eV 电阻材料的功能。

公开(公告)号：US20070278574A1

公开(公告)日：2007-12-06

申请号：US11443144

申请日：2006-05-30

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/7624

摘要： A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.

摘要翻译： 提供了一种用热软性绝缘体形成硅化合物半导体（Si）晶片的方法。 该方法形成Si衬底，具有覆盖Si衬底的热软绝缘层。 形成刚好覆盖在热软绝缘体层上的氧化硅层，顶部Si层覆盖在氧化硅上，并且晶格失配缓冲层覆盖在顶部Si层上。 形成覆盖晶格失配缓冲层的化合物半导体层。 该热软绝缘体的液相温度低于Si和化合物半导体的液相温度。 例如，热软绝缘体可以具有在约500℃至900℃的范围内的流动温度，其中流动温度大于固相温度并且小于液相温度。

公开(公告)号：US07303971B2

公开(公告)日：2007-12-04

申请号：US11184660

申请日：2005-07-18

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

摘要翻译： 提供金属/半导体/金属（MSM）二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极，存储器电阻器底部电极上方的存储器电阻器材料，以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极，半导体层覆盖在MSM底部电极上，并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt，Ir，Au，Ag，TiN或Ti的材料。 MSM顶部电极可以是诸如Pt，Ir，Au，TiN，Ti或Al的材料。 半导体层可以是非晶Si，ZnO 2或InO 2。

公开(公告)号：US07297642B2

公开(公告)日：2007-11-20

申请号：US11334015

申请日：2006-01-18

申请人： Wei Gao ,  Tingkai Li ,  Robert A. Barrowcliff ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Robert A. Barrowcliff ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L21/31

CPC分类号： H05B33/145 ,  H01L21/3115 ,  H01L31/03046 ,  Y02E10/544

摘要： A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土（RE）元素掺杂硅（Si）氧化物膜的方法。 该方法包括：提供嵌入有第一稀土元素的Si的第一靶; 提供Si的第二个目标; 共溅射第一和第二个目标; 在掺杂有第一稀土元素的衬底上形成富Si氧化硅（SRSO）膜; 并对稀土元素掺杂的SRSO膜退火。 第一靶用铒（Er），镱（Yb），铈（Ce），镨（Pr）或铽（Tb）等稀土元素掺杂。 溅射功率在约75至300瓦（W）的范围内。 不同的溅射功率被应用于两个目标。 此外，可以通过改变两个目标的有效面积来控制沉积。 例如，其中一个目标可以被部分覆盖。