公开(公告)号：US06184061B2

公开(公告)日：2001-02-06

申请号：US09166908

申请日：1998-10-06

申请人： Qiang Wu ,  Yoshihiro Tomita

发明人： Qiang Wu ,  Yoshihiro Tomita

IPC分类号： H01L2128

CPC分类号： H05K3/244 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043

摘要： An electrode of a semiconductor device comprising: a pad; an electroless diffusion prevention film formed on a surface of the pad for preventing material of the pad from diffusing; a solder precoat film formed on a surface of the electroless diffusion prevention film, and having a thickness not larger than a predetermined value, for preventing a solder bump on the solder precoat film from defective breaking; and a predetermined intermetallic compound layer formed in the solder precoat film in the vicinity of a boundary surface between the solder precoat film and the electroless diffusion prevention film, the intermetallic compound layer having a bonded surface bonded substantially to the whole of the surface of the electroless diffusion prevention film.

摘要翻译： 一种半导体器件的电极，包括：衬垫; 形成在所述垫的表面上用于防止所述垫的材料扩散的无电扩散防止膜; 形成在无电扩散防止膜的表面上并且具有不大于预定值的厚度的焊料预涂膜，用于防止焊料预涂膜上的焊料凸起不良断裂; 以及形成在焊料预涂层中的预定的金属间化合物层，其在焊料预涂膜和无电扩散防止膜之间的边界面附近，具有接合表面的金属间化合物层基本上与化学镀的整个表面结合 防扩散膜。

公开(公告)号：US6098460A

公开(公告)日：2000-08-08

申请号：US727302

申请日：1996-10-08

申请人： Tetsuro Otsuchi ,  Masato Sugimoto ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Osamu Kawasaki

发明人： Tetsuro Otsuchi ,  Masato Sugimoto ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Osamu Kawasaki

IPC分类号： G01R31/26 ,  G01L5/00 ,  G01P1/12 ,  G01P15/08 ,  G01P15/09 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66

CPC分类号： G01P15/0891 ,  G01L5/0052 ,  G01P1/127 ,  G01P15/0802 ,  G01P15/0922 ,  G01R31/2834 ,  G01R31/30 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/49789

摘要： A small accelaration sensor which is highly sensitive over a large frequency region and which varies little in characteristics such as sensitivity. A piezoelectric element is formed by connecting two main faces of retangular LiNbO.sub.3 piezoelectric substrates, in which the polarization axes are directed oppositely. Supporters comprising LiNbO.sub.3 directly connected to one end of the piezoelectric element. Eletrodes of chromium-gold being 0.2 .mu.m are thick are successively connected to the two main faces of the piozoelectric element and to the supporters, thus to produce a cantilever structure bimorph electromechanical transducer.

摘要翻译： 一种小型加速传感器，在大频率区域内具有高灵敏度，灵敏度等特性变化不大。 压电元件通过连接偏振轴相对地指向的矩形LiNbO 3压电基板的两个主面而形成。 包含直接与压电元件的一端连接的LiNbO 3的支撑体。 铬 - 金的0.2微米厚的铁素体连续地连接到波氮元素的两个主面和支撑体上，从而产生悬臂结构双压电晶片机电换能器。

公开(公告)号：US5986336A

公开(公告)日：1999-11-16

申请号：US127609

申请日：1998-07-31

申请人： Yoshihiro Tomita

发明人： Yoshihiro Tomita

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/04 ,  H01L23/28 ,  H01L23/34

CPC分类号： H01L23/49568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815

摘要： A semiconductor device includes a semiconductor element, a mounting pad on which the semiconductor element is mounted; first internal leads electrically connected to the semiconductor element; a heat radiation plate spaced from and opposite the semiconductor element with the mounting pad and located between the heat radiation plate and the semiconductor element, the heat radiation plate having a second internal lead; a sealing material encapsulating the semiconductor element, the mounting pad, the first and second internal leads, and part of the heat radiation plate; external leads continuing from the first internal leads and extending outside of the sealing material; and a grounding lead continuous with and extending from the second internal lead of the heat radiation plate, outside of the sealing material, for mechanically mounting and electrically grounding the heat radiation plate.

摘要翻译： 半导体器件包括半导体元件，安装有半导体元件的安装焊盘; 电连接到半导体元件的第一内部引线; 与所述安装焊盘间隔开并与所述半导体元件相对并位于所述散热板和所述半导体元件之间的散热板，所述散热板具有第二内部引线; 封装半导体元件，安装垫，第一和第二内部引线以及散热板的一部分的密封材料; 外部引线从第一内部引线继续并延伸到密封材料外部; 以及与散热板的第二内部引线连接并从密封材料的外部延伸的接地引线，用于机械地安装和电接地散热板。

公开(公告)号：US5982010A

公开(公告)日：1999-11-09

申请号：US976452

申请日：1997-11-25

申请人： Akihiko Namba ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Kazuo Eda

发明人： Akihiko Namba ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Kazuo Eda

IPC分类号： H01L41/22 ,  H01L41/312 ,  H01L41/338 ,  H03H3/02 ,  H01L29/84

CPC分类号： H03H3/02 ,  H01L41/312 ,  H01L41/338

摘要： A piezoelectric device is manufactured by: (1) mirror finishing surfaces of a first substrate and a second substrate made of a piezoelectric element; (2) forming grooves on at least one of the two surfaces of the first and second substrates; (3) joining the mirror-finished surfaces of the first substrate and the second substrate; (4) applying heat to the joined substrates and bonding them; (5) forming an opening on the first substrate so that a part of the exposed areas of the second substrate is exposed through the opening; (6) forming piezoelectric devices by forming electrodes on at least one of the second substrate through the opening and a corresponding area to the exposed area on the rear side of the second substrate; and (7) dividing the bonded substrates into portions each having one of the piezoelectric devices. Through this manufacturing method, piezoelectric devices with high yield ratios and high reliability can be obtained.

摘要翻译： 压电器件通过以下制造：（1）第一衬底和由压电元件制成的第二衬底的镜面精加工表面; （2）在第一和第二基板的两个表面中的至少一个上形成凹槽; （3）连接第一基板和第二基板的镜面抛光面; （4）向接合的基片施加热量并将其粘合; （5）在所述第一基板上形成开口，使得所述第二基板的所述暴露区域的一部分通过所述开口露出; （6）通过在所述第二基板中的至少一个上通过所述开口形成电极并形成与所述第二基板的后侧上的暴露区域相对应的区域来形成压电装置; 和（7）将接合的衬底分成各自具有一个压电器件的部分。 通过该制造方法，可以获得高屈服比和高可靠性的压电装置。

公开(公告)号：US5724726A

公开(公告)日：1998-03-10

申请号：US614552

申请日：1996-03-13

申请人： Yoshihiro Tomita ,  Naoto Ueda ,  Yoshirou Nishinaka ,  Shunichi Abe ,  Hideyuki Ichiyama

发明人： Yoshihiro Tomita ,  Naoto Ueda ,  Yoshirou Nishinaka ,  Shunichi Abe ,  Hideyuki Ichiyama

IPC分类号： H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01R43/00

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/85207 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  Y10T29/49121 ,  Y10T29/49146 ,  Y10T29/49172

摘要： A method of making a semiconductor device having a lead-on-chip structure includes bending a die pad extending from an outer frame outwardly from the outer frame. Thereafter, with the die pad in a convenient position, a semiconductor chip is die-bonded to the die pad. Thereafter, the die pad is bent back toward the outer frame so that it is generally parallel to but spaced from the outer frame with leads extending from the outer frame being generally parallel to the semiconductor chip. Electrodes of the semiconductor chip are connected by wire-bonding to the leads extending from the outer frame. After resin molding, the outer frame lying outside the resin package is severed and removed, completing the lead-on-chip semiconductor device.

摘要翻译： 制造具有芯片上芯片结构的半导体器件的方法包括从外框架向外弯曲从外框延伸的芯片焊盘。 此后，当芯片焊盘处于便利位置时，半导体芯片被芯片焊接到芯片焊盘。 此后，芯片焊盘向外框架弯曲，使得它大致平行于外框架，但与外框架大致平行于半导体芯片延伸。 半导体芯片的电极通过引线接合连接到从外框延伸的引线。 在树脂成型之后，将位于树脂封装外部的外框切断并移除，从而完成了片上半导体器件。

公开(公告)号：US5698471A

公开(公告)日：1997-12-16

申请号：US646451

申请日：1996-05-07

申请人： Akihiko Namba ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Kazuo Eda

发明人： Akihiko Namba ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita ,  Kazuo Eda

IPC分类号： H01L41/312 ,  H01L41/39 ,  H03H3/02 ,  H03H9/05 ,  H03H9/19 ,  H01L21/56 ,  H01L21/463

CPC分类号： H03H9/0519 ,  H01L41/312 ,  H03H3/04 ,  H03H9/19 ,  Y10S148/012 ,  Y10T156/1052 ,  Y10T156/1082

摘要： A method of manufacturing a composite substrate and the composite substrate manufactured thereby wherein surfaces of first and second substrates having different thermal expansion coefficients are mirror finished and layered on each other. A first heat treatment is applied after which a part of the second substrate is removed to a depth sufficient to expose the first substrate. A final second heat treatment directly bonds the substrates.

摘要翻译： 一种制造复合基板的方法和由此制造的复合基板，其中具有不同热膨胀系数的第一和第二基板的表面被镜面化并且彼此层叠。 施加第一热处理之后，将第二基板的一部分去除足以露出第一基板的深度。 最终的第二次热处理直接粘合基材。

公开(公告)号：US5666008A

公开(公告)日：1997-09-09

申请号：US708559

申请日：1996-09-06

申请人： Yoshihiro Tomita ,  Akiyoshi Sawai ,  Katsunori Asai

发明人： Yoshihiro Tomita ,  Akiyoshi Sawai ,  Katsunori Asai

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3107 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351

摘要： A semiconductor device for life enhancement of electrical connections between a semiconductor chip and a mounting substrate. Protruding electrodes, each including a bump electrode and a land electrode, are located on the lower surface of an LSI chip. The bump electrodes are substantially spherical and have a first thickness. Connecting terminals of substantially spherical configuration and having a second thickness are directly connected to corresponding land electrodes by melting. Connecting patterns are located on the upper surface of a wiring board which is larger in area than the LSI chip in plan configuration, and external electrodes, each including a connecting pattern and an external electrode, are located on the lower surface of the wiring board. The external electrodes are substantially spherical and have a third thickness. The connecting patterns are directly connected to corresponding connecting terminals, respectively, by melting.

摘要翻译： 一种用于半导体芯片和安装基板之间的电连接寿命增强的半导体器件。 每个包括凸起电极和焊盘电极的突起电极位于LSI芯片的下表面上。 凸起电极基本上是球形的并且具有第一厚度。 具有大致球形并且具有第二厚度的连接端子通过熔化直接连接到相应的焊盘电极。 连接图案位于布置板的上表面上，其面积比平面构造中的LSI芯片大，并且包括连接图案和外部电极的外部电极位于布线板的下表面上。 外部电极基本上是球形并具有第三厚度。 连接图案分别通过熔化直接连接到相应的连接端子。

公开(公告)号：US5647932A

公开(公告)日：1997-07-15

申请号：US601539

申请日：1996-02-14

申请人： Yutaka Taguchi ,  Kazuo Eda ,  Akihiro Kanaboshi ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita

发明人： Yutaka Taguchi ,  Kazuo Eda ,  Akihiro Kanaboshi ,  Tetsuyoshi Ogura ,  Yoshihiro Tomita

IPC分类号： H03H3/02 ,  H01L21/30 ,  H01L21/304 ,  H01L21/306

CPC分类号： H03H3/02 ,  Y10S148/012 ,  Y10S148/135

摘要： The following steps are performed when processing electronic components such as piezoelectric devices. At Step 1 inter-atom bond is created between a functional member such as a quartz crystal plate and a first substrate, and the functional member and the quartz crystal plate are directly joined together. At Step 2, the functional member and a second substrate are fixed together with an adhesive agent or by a direct bond. At Step 3, the first substrate is removed chemically or mechanically, with said functional member and said second substrate still being joined together. A step of polishing said functional member for the adjustment of thickness thereof may be done between Step 1 and Step 2. For example, a silicon dioxide thin film may be provided between the functional member and the first substrate. Since no adhesive layer exists between the functional member and the first substrate, this improves the degree of plane of the functional member when joined to the first substrate. Therefore, functional member thickness accuracy becomes extremely high and mass productivity is also improved.

摘要翻译： 在处理诸如压电装置的电子部件时执行以下步骤。 在步骤1中，在诸如石英晶体板的功能部件和第一基板之间产生原子间键合，并且功能部件和石英晶体板直接接合在一起。 在步骤2中，功能部件和第二基板通过粘合剂或直接粘合固定在一起。 在步骤3中，第一衬底被化学或机械地移除，所述功能构件和所述第二衬底仍然连接在一起。 可以在步骤1和步骤2之间进行用于调整其厚度的抛光所述功能部件的步骤。例如，可以在功能部件和第一基板之间设置二氧化硅薄膜。 由于在功能部件和第一基板之间不存在粘接层，因此能够提高与第一基板接合时的功能部件的平面度。 因此，功能元件厚度精度变得非常高，并且也提高了批量生产率。

公开(公告)号：US20170287847A1

公开(公告)日：2017-10-05

申请号：US15088857

申请日：2016-04-01

申请人： Rajendra C. Dias ,  Robert L. Sankman ,  Joshua D. Heppner ,  Mitul B. Modi ,  Yoshihiro Tomita

发明人： Rajendra C. Dias ,  Robert L. Sankman ,  Joshua D. Heppner ,  Mitul B. Modi ,  Yoshihiro Tomita

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3025

摘要： Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.

公开(公告)号：US08518750B2

公开(公告)日：2013-08-27

申请号：US13734861

申请日：2013-01-04

申请人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

发明人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

IPC分类号： H01L21/00

CPC分类号： H01L21/4867 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/5389 ,  H01L24/24 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.