公开(公告)号：US07266014B2

公开(公告)日：2007-09-04

申请号：US11161359

申请日：2005-08-01

申请人： Chao-I Wu ,  Ming-Hsiu Lee

发明人： Chao-I Wu ,  Ming-Hsiu Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/18

摘要： A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

摘要翻译： 提供了一种操作非易失性存储器的方法，其中非易失性存储器至少包括：通过层叠隧穿介电层，电荷俘获层，电介质层和栅极导电层顺序地形成的栅极结构，以及源极 区域和漏极区域。 当执行操作方法时，紫外线照射到非易失性存储器以将电子注入电荷捕获层以擦除非易失性存储器，并且向栅极导电层施加负电压，并且正电压为 施加到漏极区域以通过频带带诱导的热空穴注入对非易失性存储器进行编程。

公开(公告)号：US20070132000A1

公开(公告)日：2007-06-14

申请号：US11302738

申请日：2005-12-13

申请人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Ming-Hsiu Lee

发明人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Ming-Hsiu Lee

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7923

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储单元包括跨门，载流子俘获结构和至少两个源/漏区。 跨门位于基板上，跨越垂直翅片结构。 载体捕获结构位于跨门和衬底之间，其中载流子俘获结构包括直接与跨骑门接触的捕获层和位于俘获层和基底之间的隧道层。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US20060284243A1

公开(公告)日：2006-12-21

申请号：US11146777

申请日：2005-06-06

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/7885 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/90

摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.

摘要翻译： 不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。 复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。 非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。 非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。 还描述了制造非对称掺杂的存储单元的方法。

公开(公告)号：US07038928B1

公开(公告)日：2006-05-02

申请号：US10991537

申请日：2004-11-17

申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

IPC分类号： G11C17/00

CPC分类号： G11C16/12 ,  G11C16/0475 ,  G11C16/26

摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)−I1(VgO)).

摘要翻译： 描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。 存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是 测量，其中Vg是栅极电压。 绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。 确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

公开(公告)号：US09019771B2

公开(公告)日：2015-04-28

申请号：US13661723

申请日：2012-10-26

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0475 ,  G11C16/10

摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

摘要翻译： 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US08824188B2

公开(公告)日：2014-09-02

申请号：US13567750

申请日：2012-08-06

申请人： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

发明人： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/77

摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

摘要翻译： 提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。 存储器件的操作方法包括以下步骤。 使存储器件处于置位状态。 用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。 读取设置状态的存储器件。 一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。 将恢复的偏置电压施加到存储器件。 在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

公开(公告)号：US08809829B2

公开(公告)日：2014-08-19

申请号：US12484955

申请日：2009-06-15

申请人： Ming-Hsiu Lee

发明人： Ming-Hsiu Lee

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.

摘要翻译： 具有在有源区域中具有改变的化学计量的相变材料元件的存储器件在设定状态电阻中不会出现漂移。 一种用于制造存储器件的方法包括：首先制造集成电路，该集成电路包括具有大体积化学计量的相变材料体的相变存储器单元的阵列; 然后将成形电流施加到阵列中的相变存储器单元，以将相变材料的主体的有源区域中的主体化学计量改变为改变的化学计量，而不会干扰有源区域外的主体化学计量。 主要化学计量学的特征在于在活性区域外的热力学条件下的稳定性，而改性的化学计量学的特征在于活性区域内的热力学条件下的稳定性。

公开(公告)号：US08743599B2

公开(公告)日：2014-06-03

申请号：US13421718

申请日：2012-03-15

申请人： Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

发明人： Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641 ,  H01L45/1675

摘要： A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

摘要翻译： 存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。 一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。 该方法包括改变相变材料的第一有界区域的开关体积的化学成分。 该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如 第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。 第一保留性与第二保留性不同。

公开(公告)号：US08426294B2

公开(公告)日：2013-04-23

申请号：US13476964

申请日：2012-05-21

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

IPC分类号： H01L29/76

CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US08350316B2

公开(公告)日：2013-01-08

申请号：US12471287

申请日：2009-05-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

IPC分类号： H01L29/732

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。