Abstract:
Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.
Abstract:
The invention is a pervaporation process and pervaporation equipment, using a series of membrane modules, and including inter-module reheating of the feed solution under treatment. The inter-module heating is achieved within the tube or vessel in which the modules are housed, thereby avoiding the need to repeatedly extract the feed solution from the membrane module train.
Abstract:
A method for fabricating an IBIIIAVIA-group amorphous compound used for thin-film solar cells is provided. A mixture solution including elements of Group IB, IIIA, VIA or combinations thereof is provided. The mixture solution is heated and filtered. IBIIIAVIA-group amorphous powders are acquired after drying the heated and filtered mixture solution.
Abstract:
A method for processing a video sequence having a plurality of frames includes the steps of: extracting features from each of the frames, determining correspondences between the extracted features from two of the frames, estimating motion in the video sequence based on the determined correspondences, generating a background mosaic for the video sequence based on the estimated motion, and performing foreground-background segmentation on each of the frames based on the background mosaic.
Abstract:
A mounting apparatus for mounting a card reader that defines a fixing hole in a sidewall thereof, and forms a first connector in a rear wall thereof, includes a chassis, a bracket slidably mounted to the chassis, a pair of first resilient members, and a locking member. The chassis includes a front wall defining a first opening for the card reader passing therethrough. A second connector is mounted to the bracket, corresponding to the first connector of the card reader. The first resilient members are connected between the chassis and the bracket. The first resilient members are stretched when mounting the card reader. The locking member includes a retaining member mounted to the chassis, and a securing member mounted to the retaining member via a second resilient member. The securing member includes a securing portion protruding therefrom for engaging with the fixing hole of the card reader.
Abstract:
A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.
Abstract:
An implementation provides a method including forming a metric surface in a particle-based framework for tracking an object, the metric surface relating to a particular image in a sequence of digital images. Multiple hypotheses are formed of a location of the object in the particular image, based on the metric surface. The location of the object is estimated based on probabilities of the multiple hypotheses.
Abstract:
Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain.
Abstract:
A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.