公开(公告)号：US08461640B2

公开(公告)日：2013-06-11

申请号：US12555756

申请日：2009-09-08

Applicant: Yaw Wen Hu ,  Prateep Tuntasood

Inventor： Yaw Wen Hu ,  Prateep Tuntasood

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7881

Abstract: A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate.

Abstract translation: 非易失性存储单元具有在衬底层上具有第一导电类型的鳍状半导体构件的衬底层。 翅片状构件具有第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，并且在第一区域和第二区域之间延伸的沟道区域。 翅片状构件具有顶表面和在第一区域和第二区域之间的两个侧表面。 字线与第一区域相邻并且电容耦合到沟道区域的第一部分的顶表面和两个侧表面。 浮动栅极与字线相邻并且与顶表面绝缘并且电容耦合到沟道区的第二部分的两个侧表面。 耦合栅极电容耦合到浮动栅极。 擦除栅极与第二区域绝缘并且与浮栅和耦合栅极相邻。

公开(公告)号：US08456904B2

公开(公告)日：2013-06-04

申请号：US13172599

申请日：2011-06-29

Applicant: Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

Inventor： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

IPC: G11C11/36

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract translation: 各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。 可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。 体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。 各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。 电路可以包括在存储器系统中。

公开(公告)号：US08384147B2

公开(公告)日：2013-02-26

申请号：US13097766

申请日：2011-04-29

Applicant: Nhan Do ,  Amitay Levi

Inventor： Nhan Do ,  Amitay Levi

IPC: H01L29/792 ,  H01L29/788 ,  G11C7/00

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first cooductivity type The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed.

Abstract translation: 公开了电可编程和可擦除存储单元的系统。 在一个示例性实施方式中，单元可以在第一共同类型的半导体材料的衬底中具有两个存储晶体管。第一存储晶体管是具有第一区域的类型和在衬底中的每个第二导电类型的第二存储晶体管第二存储晶体管 存储晶体管是在基板中具有第三区域和第四导电类型的第四区域的类型。 还公开了由这样的存储器单元和非易失性存储单元形成的阵列。

公开(公告)号：US08258065B2

公开(公告)日：2012-09-04

申请号：US12581783

申请日：2009-10-19

Applicant: Bomy Chen ,  Long Ching Wang ,  Sychyi Fang

Inventor： Bomy Chen ,  Long Ching Wang ,  Sychyi Fang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5389 ,  H01L28/10 ,  H01L28/91 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract translation: 公开了与半导体制品相关联的系统和方法，包括在衬底上形成第一材料层，在限定第一层中的无源元件的区域内蚀刻沟槽，在沟槽的侧壁上形成金属区域，以及形成电介质区域 聚合物材料在衬底上或衬底中。 此外，示例性方法还可以包括在沟槽的侧壁上形成金属区域的区域，使得这些区域的平面条带部分形成无源元件的导电区域，该无源元件相对于主要平面基本上垂直地排列 底物。 其它示例性实施例可以包括与本文所阐述的创新的一个或多个方面一致的各种物品或方法，包括电容和/或感应方面，基于钛和/或钽的电阻方面，产品，通过工艺，封装和复合材料的产品。

公开(公告)号：US08164135B2

公开(公告)日：2012-04-24

申请号：US12773811

申请日：2010-05-04

Applicant: Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

Inventor： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC: H01L29/788

CPC classification number: G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

Abstract: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Abstract translation: 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US20120074923A1

公开(公告)日：2012-03-29

申请号：US13306950

申请日：2011-11-29

Applicant: Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

Inventor： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC: G05F3/16

CPC classification number: H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract translation: 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US08138524B2

公开(公告)日：2012-03-20

申请号：US11592104

申请日：2006-11-01

Applicant: Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

Inventor： Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L29/42324 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.

Abstract translation: 一种形成浮栅存储器单元阵列的方法及由此形成的阵列，其中每个存储单元包括具有第一导电类型的半导体材料的衬底，形成在衬底中的源极和漏极区，设置在该衬底上的导电材料块 并且电连接到源极，以及浮置栅极，其具有设置在源极区域上方并与源极区域绝缘的第一部分以及设置在沟道区域上方并与沟道区域绝缘的第二部分。 浮动栅极第一部分包括倾斜的上表面和在锐边处相遇的侧表面。 导电控制栅极设置在沟道区之上并与沟道区绝缘以控制其导电性。

公开(公告)号：US20120044774A1

公开(公告)日：2012-02-23

申请号：US13286166

申请日：2011-10-31

Applicant: Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

Inventor： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

IPC: G11C7/06 ,  H03F3/45

CPC classification number: G11C11/5642 ,  G11C7/06 ,  G11C7/062

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract translation: 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

公开(公告)号：US08094511B2

公开(公告)日：2012-01-10

申请号：US12623259

申请日：2009-11-20

Applicant: Douglas J. Lee ,  Cindy Ho Malamy ,  Kyle McMartin ,  Tam Minh Nguyen ,  Jih Min Niu ,  Hung Thanh Nguyen ,  Thuc Tran Bui ,  Conrado Canlas Canio ,  Richard Zimering

Inventor： Douglas J. Lee ,  Cindy Ho Malamy ,  Kyle McMartin ,  Tam Minh Nguyen ,  Jih Min Niu ,  Hung Thanh Nguyen ,  Thuc Tran Bui ,  Conrado Canlas Canio ,  Richard Zimering

IPC: G11C7/00

CPC classification number: G11C8/10 ,  G11C5/066 ,  G11C8/04 ,  G11C8/06 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit.

Abstract translation: 非易失性存储器件包括用于接收多个信号的接口电路。 多个信号以串行格式提供复用的地址和数据以及命令信号。 输入缓冲器存储以串行格式接收的多个信号，并重构地址，数据和命令信号，并具有输出。 命令电路接收输入缓冲器的输出并存储命令信号。 地址电路接收输入缓冲器的输出并存储地址信号。 数据缓冲电路接收输入缓冲器的输出并存储数据信号。 一组非易失性存储单元响应于来自地址解码器的地址信号而存储数据并向数据缓冲器提供数据。 状态机连接到命令电路并控制非易失性存储单元的阵列。 输出缓冲器从数据缓冲器电路接收数据，并向接口电路提供数据。

公开(公告)号：US20110296276A1

公开(公告)日：2011-12-01

申请号：US12791774

申请日：2010-06-01

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/3715 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6337

Abstract: An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port. A bus connects to each of the storage circuits and to each other and supplies data bits between each storage circuit and between the nonvolatile memory and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the plurality of data bits; or the plurality of corrected data bits, and supplies same to the input/output port of the associated storage circuit and stores same as storage bits in the storage circuit, and supplies the storage bits as output of the storage circuit.

Abstract translation: 用于非易失性存储器的输出缓冲器电路存储与多个数据位相关联的多个数据位和多个纠错校验（“ECC”）位。 输出缓冲器电路包括用于接收多个数据位和多个ECC位的错误检查电路，以确定是否需要校正多个数据位。 错误检查电路提供多个数据位作为其输出，并产生校正信号。 误差校正电路接收多个数据命中和多个ECC位，并响应于校正信号产生多个校正数据位。 输出缓冲电路还具有三个或更多个存储电路，每个存储电路具有输入/输出端口。 总线连接到每个存储电路和彼此之间，并且在每个存储电路之间以及非易失性存储器和存储电路之间提供数据位，并且提供数据位作为输出缓冲器电路的输出。 开关电路与每个存储电路相关联，用于接收多个数据位; 或多个校正数据位，并将其提供给相关联的存储电路的输入/输出端口，并将其存储在存储电路中，并将存储位作为存储电路的输出提供。