-
公开(公告)号：US12125706B2
公开(公告)日：2024-10-22
申请号：US18331387
申请日：2023-06-08
发明人： Chun-Yen Peng , Te-Yang Lai , Sai-Hooi Yeong , Chi On Chui
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3115 , H01L21/8234 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/02356 , H01L21/28158 , H01L21/3115 , H01L21/823431 , H01L21/823462 , H01L29/517 , H01L29/66795 , H01L29/785
摘要： A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions may be modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.
-
公开(公告)号：US12124785B2
公开(公告)日：2024-10-22
申请号：US18448115
申请日：2023-08-10
发明人： Jia-Hong Gao , Hui-Zhong Zhuang
IPC分类号： G06F30/30 , G06F30/392 , H01L21/04 , H01L27/02
CPC分类号： G06F30/392 , H01L21/041 , H01L27/0207
摘要： A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.
-
公开(公告)号：US12124168B2
公开(公告)日：2024-10-22
申请号：US17557146
申请日：2021-12-21
发明人： Jing Chang , Ching-Hai Yang , Wei-Hsiang Tseng
CPC分类号： G03F7/16 , G05B13/027 , G06T7/001 , G06T7/60 , H01L21/0273 , H01L22/20 , H04N23/90 , G06T2207/20081 , G06T2207/20084 , G06T2207/30148
摘要： A method for manufacturing a semiconductor device includes obtaining a first image of a fluid dispense nozzle using a first camera, the fluid dispense nozzle configured to dispense fluid on a semiconductor substrate, obtaining a second image of the fluid dispense nozzle using a second camera, the second image having a higher resolution than the first image, determining a width of the fluid dispense nozzle at multiple intervals along the fluid dispense nozzle and a width of a spray pattern of a fluid being dispensed from the fluid dispense nozzle at multiple intervals along the spray pattern, fitting a first straight line to a series of data points representing a plurality of widths of the intervals along the fluid dispense nozzle and a plurality of widths of the intervals along the spray pattern, determining a first slope of the first straight line, and determining a condition of the spray pattern and the fluid dispense nozzle based on the first slope.
-
公开(公告)号：US12124119B2
公开(公告)日：2024-10-22
申请号：US18166472
申请日：2023-02-08
发明人： Lan-Chou Cho , Chewn-Pu Jou , Feng-Wei Kuo , Huan-Neng Chen , Min-Hsiang Hsu
CPC分类号： G02F1/025 , G02F1/0151 , G02F2201/302
摘要： An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.
-
公开(公告)号：US20240349508A1
公开(公告)日：2024-10-17
申请号：US18751331
申请日：2024-06-23
摘要： A method of forming a device includes the following steps. A multi-layer stack is formed, wherein the multi-layer stack includes a plurality of dielectric layers and a plurality of first sacrificial layers stacked alternately. A first trench is formed in the multi-layer stack. A memory material layer is formed on a sidewall of the first trench. A channel layer is conformally on the sidewall of the first trench and over the memory material layer. A plurality of conductive pillars are formed in the first trench.
-
公开(公告)号：US20240349473A1
公开(公告)日：2024-10-17
申请号：US18643753
申请日：2024-04-23
发明人： Hidehiro Fujiwara , Chia-En Huang , Yen-Huei Chen , Yih Wang
IPC分类号： H10B10/00 , G11C5/06 , H01L27/092 , H01L29/66 , H01L29/78
CPC分类号： H10B10/12 , G11C5/063 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.
-
公开(公告)号：US20240347640A1
公开(公告)日：2024-10-17
申请号：US18757165
申请日：2024-06-27
发明人： Chi-Yi Chuang , Hou-Yu Chen , Kuan-Lun Cheng
IPC分类号： H01L29/78 , H01L21/02 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/02293 , H01L21/0245 , H01L21/02532 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823487 , H01L29/6681 , H01L29/66818
摘要： A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.
-
公开(公告)号：US20240347637A1
公开(公告)日：2024-10-17
申请号：US18754900
申请日：2024-06-26
发明人： Yu-Kuan LIN , Chang-Ta YANG , Ping-Wei WANG
IPC分类号： H01L29/78 , H01L21/02 , H01L21/308 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/785 , H01L21/0228 , H01L21/3083 , H01L21/823821 , H01L27/0924 , H01L29/0649 , H01L29/4232 , H01L29/66545 , H01L29/6681
摘要： Methods for manufacturing a semiconductor device structure are provided. The method includes forming a first masking layer covering a first region and a second region and forming a second masking layer over the first masking layer, and the second masking layer includes a first pattern over the second region. The method further includes forming a third masking layer over the second masking layer, and the third masking layer includes a second pattern over the first region and transferring the second pattern of the third masking layer to the second masking layer to form a third pattern from the second masking layer. The method further includes transferring the first pattern and the third pattern of the second masking layer to the first masking layer to form a fourth pattern and a fifth pattern from the first masking layer over the first region and the second region, respectively.
-
公开(公告)号：US20240347635A1
公开(公告)日：2024-10-17
申请号：US18751953
申请日：2024-06-24
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/0665 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. The dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.
-
公开(公告)号：US20240347624A1
公开(公告)日：2024-10-17
申请号：US18753469
申请日：2024-06-25
发明人： Jin-Mu Yin , Wei-Yang Lee , Chih-Hao Yu , Yen-Ting Chen , Chia-Pin Lin
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66553 , H01L29/42392 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.
-
-
-
-
-
-
-
-
-
搜索结果
32460 条记录 (耗时 0.084 秒)
