公开(公告)号：US20140284770A1

公开(公告)日：2014-09-25

申请号：US14347443

申请日：2011-09-28

申请人： Meoung Whan Cho ,  Seog Woo Lee ,  Ryuichi Toba ,  Yoshitaka Kadowaki

发明人： Meoung Whan Cho ,  Seog Woo Lee ,  Ryuichi Toba ,  Yoshitaka Kadowaki

IPC分类号： H01L33/00 ,  H01L33/20 ,  H01L21/02 ,  H01L21/78 ,  H01L29/06

CPC分类号： H01L33/0075 ,  H01L21/02365 ,  H01L21/78 ,  H01L29/0603 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20

摘要： The method of manufacturing a semiconductor device according to the present invention includes: a step of forming a semiconductor laminate on a growth substrate with a lift-off layer therebetween; a step of providing grooves in a grid pattern in the semiconductor laminate, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape; a step of forming a conductive support body; and a step of removing the lift-off layer using a chemical lift-off process, in which step, in supplying an etchant to the grooves via through-holes provided in a portion above the grooves, the lift-off layer is etched from only one side surface of each semiconductor structure.

摘要翻译： 根据本发明的制造半导体器件的方法包括：在其上具有剥离层的生长衬底上形成半导体层叠体的步骤; 在半导体层叠体中设置栅格图案的槽，由此形成多个具有近似四边形横截面形状的半导体结构; 形成导电性支撑体的工序; 以及使用化学剥离处理去除剥离层的步骤，其中通过设置在沟槽上方的通孔的沟槽向槽施加蚀刻剂，仅剥离层仅从蚀刻 每个半导体结构的一个侧表面。

公开(公告)号：US20140167218A1

公开(公告)日：2014-06-19

申请号：US13720042

申请日：2012-12-19

申请人： Shekar Mallikarjunaswamy ,  Madhur Bobde

发明人： Shekar Mallikarjunaswamy ,  Madhur Bobde

IPC分类号： H01L27/02 ,  H01L23/60 ,  H01L21/02 ,  H01L29/73

CPC分类号： H01L27/0248 ,  H01L21/02365 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/7304 ,  H01L29/7322 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

摘要翻译： 垂直TVS（VTVS）电路包括用于在其上支撑VTVS器件的半导体衬底，其具有延伸到衬底底部的重掺杂层。 提供深沟槽用于多声道VTVS之间的隔离。 还提供沟槽门，以增加集成EMI滤波器的VTVS电容。

公开(公告)号：US20140167174A1

公开(公告)日：2014-06-19

申请号：US13717532

申请日：2012-12-17

申请人： Munkang Choi ,  Victor Moroz ,  Xi-Wei Lin

发明人： Munkang Choi ,  Victor Moroz ,  Xi-Wei Lin

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L21/02365 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.

摘要翻译： 粗略地描述，集成电路晶体管结构具有半导体材料体，该主体具有两个纵向间隔开的掺杂源极/漏极体积，其间具有通道，位于主体外部并面向主体的至少一个表面的栅极堆叠 这个频道。 主体在通道容积内纵向地包含调节体积，并且在第一表面之后隔开第一距离并且与源/排出体积纵向隔开。 调节体积包括至少在晶体管处于截止状态时在每个纵向位置处具有不同于相同主体材料在同一纵向位置的电导率的调节体积材料。 在一个实施例中，调节体积材料是电介质。 在另一个实施例中，调节体积材料是电导体。

公开(公告)号：US08686474B2

公开(公告)日：2014-04-01

申请号：US13740733

申请日：2013-01-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC分类号： H01L21/02 ,  H01L29/12

CPC分类号： H01L21/02365 ,  H01L21/02104 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02645 ,  H01L29/12

摘要： A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.

摘要翻译： 一种结构包括衬底，掩模，缓冲/成核层和III-V族化合物半导体材料。 衬底具有顶表面并且具有从顶表面的凹陷。 凹部包括侧壁。 第一个掩模是基板的顶面。 缓冲/成核层沿着侧壁，并且具有与侧壁的材料组成不同的材料组成。 III-V族化合物半导体材料从缓冲层/成核层上的凹部内部连续地延伸到第一掩模之上。

公开(公告)号：US20140061748A1

公开(公告)日：2014-03-06

申请号：US13716078

申请日：2012-12-14

申请人： SK HYNIX INC.

发明人： Dong Kee LEE

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/78 ,  H01L21/02365 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral region, a gate pattern formed over the substrate in the peripheral region, a multilayered structure formed over the gate pattern in the peripheral region, the multilayered structure including interlayer insulating layers and material layers for sacrificial layers, and a capping layer formed between the gate pattern and the multilayered structure in the peripheral region to cover the substrate, the capping layer configured to prevent diffusion of impurities from the material layers for the sacrificial layers into the substrate in the peripheral region.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 该器件包括：包括单元区域和外围区域的衬底;形成在周边区域中的衬底上的栅极图案;形成在周边区域中的栅极图案上的多层结构，所述多层结构包括层间绝缘层和用于 牺牲层，以及在周边区域中的栅极图案和多层结构之间形成的覆盖衬底的覆盖层，所述覆盖层被配置为防止杂质从用于牺牲层的材料层扩散到周边区域中的衬底中。

公开(公告)号：US20130221440A1

公开(公告)日：2013-08-29

申请号：US13849971

申请日：2013-03-25

申请人： NEC Corporation ,  NLT Technologies, Ltd.

发明人： Shigeru MORI

IPC分类号： H01L23/28 ,  H01L29/78 ,  H01L21/02 ,  H01L29/02

CPC分类号： H01L23/28 ,  H01L21/02365 ,  H01L29/02 ,  H01L29/66757 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.

摘要翻译： 提供一种半导体器件，其中半导体层形成在绝缘基板上，其中插入在半导体层和绝缘基板之间的前端绝缘层，其能够防止绝缘基板中包含的杂质对半导体层的作用 并提高半导体器件的可靠性。 在TFT（薄膜晶体管）中，使硼被包含在距离绝缘基板的表面约100nm以下的区域中，使得硼浓度以平均速率降低约1/1000倍/ 1 从绝缘基板的表面朝向半导体层。

公开(公告)号：US20130168833A1

公开(公告)日：2013-07-04

申请号：US13776446

申请日：2013-02-25

申请人： Hitoshi Sato ,  John F. Kaeding ,  Michael Iza ,  Benjamin A. Haskell ,  Troy J. Baker ,  Steven P. DenBaars ,  Shuji Nakamura

发明人： Hitoshi Sato ,  John F. Kaeding ,  Michael Iza ,  Benjamin A. Haskell ,  Troy J. Baker ,  Steven P. DenBaars ,  Shuji Nakamura

IPC分类号： H01L29/04 ,  H01L21/02

CPC分类号： H01L29/045 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02365 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262

摘要： A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

摘要翻译： 通过使用含有至少一些铟的（Al，In，Ga）N成核层，通过金属有机化学气相沉积（MOCVD）增强器件质量的平面半极性半导体薄膜的生长的方法。 具体地，该方法包括将衬底装载到反应器中，在氮气和/或氢气和/或氨气流下加热衬底，在加热衬底上沉积In x Ga 1-x N成核层，在半导体衬底上沉积半极性氮化物半导体薄膜 In x Ga 1-x N成核层，并在氮气过压下冷却该衬底。

公开(公告)号：US08377341B2

公开(公告)日：2013-02-19

申请号：US12100824

申请日：2008-04-10

申请人： Manchao Xiao ,  Thomas Richard Gaffney

发明人： Manchao Xiao ,  Thomas Richard Gaffney

IPC分类号： C07C395/00

CPC分类号： C23C16/06 ,  C01B19/002 ,  C07B59/004 ,  C07B2200/05 ,  C07C395/00 ,  C23C16/305 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02365 ,  H01L21/02562 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1616

摘要： Tellurium (Te)-containing precursors, Te containing chalcogenide phase change materials are disclosed in the specification. A method of making Te containing chalcogenide phase change materials using ALD, CVD or cyclic CVD process is also disclosed in the specification in which at least one of the disclosed tellurium (Te)-containing precursors is introduced to the process.

摘要翻译： 在本说明书中公开了含碲（Te）的前体，含Te的硫族化物相变材料。 在本说明书中还公开了使用ALD，CVD或循环CVD工艺制备含有硫族化物相变材料的Te的方法，其中将至少一种所公开的含碲（Te）的前体引入该方法。

公开(公告)号：US20120132921A1

公开(公告)日：2012-05-31

申请号：US12956145

申请日：2010-11-30

申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L21/18

CPC分类号： H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02658 ,  H01L29/66446 ,  H01L29/66522 ,  H01L33/007

摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有相对的第一和第二侧面的硅衬底。 第一和第二面中的至少一个包括硅（111）表面。 该方法包括在硅衬底的第一侧上形成高的热膨胀系数（CTE）层。 高CTE层的CTE大于硅的CTE。 该方法包括在硅衬底的第二侧上形成缓冲层。 缓冲层的CTE大于硅的CTE。 该方法包括在缓冲层上形成III-V族层。 III-V族层的CTE大于缓冲层的CTE。

公开(公告)号：US20110115010A1

公开(公告)日：2011-05-19

申请号：US12943126

申请日：2010-11-10

申请人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

发明人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

IPC分类号： H01L27/11

CPC分类号： H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

摘要翻译： 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。