公开(公告)号：US20150145014A1

公开(公告)日：2015-05-28

申请号：US14471778

申请日：2014-08-28

申请人： Su-Jin SHIN ,  Dong-Chul YOO ,  Ki-Hyun HWANG

发明人： Su-Jin SHIN ,  Dong-Chul YOO ,  Ki-Hyun HWANG

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L27/11563 ,  H01L27/11517 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction.

摘要翻译： 垂直存储器件包括衬底，第一电池块和第二电池块。 基板包括中心区域和周边区域。 至少一个第一细胞块位于中心区域。 第一单元块包括第一通道和第一栅极线。 至少一个第二单元块位于外围区域上。 第二单元块包括第二通道和第二栅极线。 第二单元块的宽度大于第一单元块的宽度。 第一和第二通道在垂直于衬底顶表面的第一方向上延伸。 第一栅极线围绕第一沟道并且第一栅极线在第一方向上彼此间隔开。 第二栅极线围绕第二通道并且在第一方向上彼此间隔开。

公开(公告)号：US20150144967A1

公开(公告)日：2015-05-28

申请号：US14601345

申请日：2015-01-21

申请人： ROHM CO., LTD.

发明人： Shuhei MITANI ,  Yuki NAKANO ,  Heiji WATANABE ,  Takayoshi SHIMURA ,  Takuji HOSOI ,  Takashi KIRINO

IPC分类号： H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/7827 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0445 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1087 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.

摘要翻译： 半导体器件包括由第一导电型SiC制成的半导体层; 形成在半导体层上并具有沟道区的第二导电类型阱区; 形成在所述阱区上并且包括邻近所述阱区的第一区和与所述第一区相邻的第二区的第一导电型源极区; 形成在所述半导体层上并具有与所述第一区域接触的第一部分的栅极绝缘膜; 第二部分，其接触所述阱区域并且具有与所述第一部分的厚度相同的厚度; 以及第三部分，其接触所述第二区域并且具有大于所述第一部分的厚度的厚度; 以及形成在栅极绝缘膜上并与通过栅极绝缘膜形成沟道的沟道区相对的栅电极。

公开(公告)号：US09041875B2

公开(公告)日：2015-05-26

申请号：US14179787

申请日：2014-02-13

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Setsuo Nakajima ,  Yasuyuki Arai

IPC分类号： G02F1/136 ,  G02F1/1368 ,  G02F1/1345 ,  H01L29/49 ,  H01L27/12 ,  G02F1/1362

CPC分类号： H01L29/511 ,  G02F1/1345 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/78669

摘要： In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

摘要翻译： 在半导体装置中，由反无交错型TFT构成的无机材料形成的第一层间绝缘层，形成在第一层间绝缘层上的由有机材料构成的第二层间绝缘层和与第一层间绝缘层形成的像素电极 第二层间绝缘层设置在基板上，并且在基板的端部上设置与另一基板的布线电连接的输入端子部。 输入端子部分包括由与栅电极相同的材料制成的第一层和由与像素电极相同的材料制成的第二层。 利用这种结构，光刻方法中使用的光掩模的数量可以减少到5个。

公开(公告)号：US09035373B2

公开(公告)日：2015-05-19

申请号：US14104656

申请日：2013-12-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Da-Yuan Lee ,  Kuang-Yuan Hsu

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L27/088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

摘要翻译： 描述了在多个器件区域中的每一个中制造具有不同栅极结构的半导体器件的方法。 该方法可以包括替换门过程。 该方法包括在形成在基板的一个或多个区域上的氧化物层上形成硬掩模层。 在第一，第二和第三器件区域中的每一个上形成高k栅介质层。 高k栅极电介质层可以直接形成在第一和第二器件区域的硬掩模层上，并直接形成在第三器件区域中形成的界面层上。 还描述了包括形成在同一衬底上的具有不同栅极电介质的多个器件（例如，晶体管）的半导体器件。

公开(公告)号：US08993400B1

公开(公告)日：2015-03-31

申请号：US14029500

申请日：2013-09-17

申请人： Cypress Semiconductor Corporation

发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William C. Koutny

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

摘要： A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

公开(公告)号：US20150069493A1

公开(公告)日：2015-03-12

申请号：US14166998

申请日：2014-01-29

申请人： Kabushiki Kaisha Toshiba

发明人： Atsushi MURAKOSHI ,  Keiichi Sawa

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66825

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer; a floating gate layer provided on the first insulating film; a second insulating film provided on the floating gate layer; and a gate electrode provided on the second insulating film, the first insulating film including silicon, oxygen, and carbon. Concentration of the carbon in a direction from the semiconductor layer side toward the floating gate layer side has a maximum between the semiconductor layer and the floating gate layer, and the maximum being located nearer to the semiconductor layer side than to the floating gate layer side.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体层; 设置在所述半导体层上的第一绝缘膜; 设置在所述第一绝缘膜上的浮栅层; 设置在所述浮栅层上的第二绝缘膜; 以及设置在所述第二绝缘膜上的栅电极，所述第一绝缘膜包括硅，氧和碳。 从半导体层侧朝向浮动栅极层的方向上的碳浓度在半导体层和浮动栅极层之间具有最大值，并且最大值比浮置栅极侧更靠近半导体层侧。

公开(公告)号：US08969165B2

公开(公告)日：2015-03-03

申请号：US14178166

申请日：2014-02-11

申请人： Intel Corporation

发明人： Willy Rachmady ,  James Blackwell

IPC分类号： H01L21/44 ,  H01L29/51 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/511 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545

摘要： A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.

摘要翻译： 一种半导体器件，包括具有包括金属栅极结构的晶体管的衬底; 形成在所述基板上的第一氧化物层; 形成在所述第一氧化物层上的硅烷层; 以及在所述金属栅极结构上生长的非导电金属氧化物层，其中所述硅烷层抑制所述非导电金属氧化物层的成核和生长。

公开(公告)号：US20150035086A1

公开(公告)日：2015-02-05

申请号：US13957991

申请日：2013-08-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

IPC分类号： H01L29/66 ,  H01L29/51

CPC分类号： H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

摘要翻译： 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

公开(公告)号：US08901674B2

公开(公告)日：2014-12-02

申请号：US13775430

申请日：2013-02-25

申请人： International Business Machines Corporation

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon ,  Christopher Carr Parks ,  Yun-Yu Wang

IPC分类号： H01L21/02 ,  H01L29/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US08889472B2

公开(公告)日：2014-11-18

申请号：US13260899

申请日：2011-04-13

申请人： Seth Miller

发明人： Seth Miller

IPC分类号： H01L51/40

CPC分类号： H01L29/517 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01G4/1218 ,  H01G4/1236 ,  H01G4/1254 ,  H01G4/1272 ,  H01G4/145 ,  H01G4/33 ,  H01L21/02118 ,  H01L28/40 ,  H01L29/408 ,  H01L29/511 ,  H01L29/78

摘要： Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.

摘要翻译： 与纳米复合介电材料相关的技术一般在此描述。 这些技术可以体现在用于制造和使用这种材料的装置，系统，方法和/或方法中。 示例性方法可以包括：提供具有多个纳米颗粒和有机介质的膜; 粉碎胶片以形成颗粒; 并将颗粒施加到基底上。 示例性方法还可以包括提供具有位于纳米颗粒之间的纳米颗粒和空隙的纳米颗粒膜; 使膜与含有机材料的蒸汽接触; 并固化有机材料以形成纳米复合电介质膜。 各种描述的技术可以提供具有优异的纳米颗粒分散体的纳米复合介电材料，其可以导致改善的介电性质。