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公开(公告)号：US20240020242A1
公开(公告)日：2024-01-18
申请号：US18362015
申请日：2023-07-31
IPC分类号： G06F12/126 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
CPC分类号： G06F12/126 , G06F2212/6042 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/128 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F12/0888
摘要： Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
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公开(公告)号：US11775446B2
公开(公告)日：2023-10-03
申请号：US17472811
申请日：2021-09-13
IPC分类号： G06F12/0811 , G06F12/02 , G06F12/0897 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/082 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
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公开(公告)号：US20230281126A1
公开(公告)日：2023-09-07
申请号：US18309893
申请日：2023-05-01
IPC分类号： G06F12/0811 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
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公开(公告)号：US11709785B2
公开(公告)日：2023-07-25
申请号：US16914201
申请日：2020-06-26
发明人： Robert Ellis , Brent Jacobs , Kevin O'Toole
CPC分类号： G06F12/1408 , G06F9/4552 , G06F12/0246 , G06F12/0853 , G06F21/602 , G06F21/78
摘要： Aspects of a storage device including a memory and an encryption core are provided. The storage device may be configured for providing secure data storage, as well as one or more post-processing operations to be performed with the data. The encryption core, which may be configured to decrypt data, may control execution of one or more post-processing operations using the data. A read command received from a host device may include a tag associated with data identified by the read command. When encrypted data is retrieved from memory according to the read command, the encryption core may decrypt the encrypted data and provide the decrypted data for post-processing based on the tag. A corresponding post-processing operation may return a result when executed using the decrypted data. Rather than raw data identified by the read command, the result may be delivered to the host device in response to the read command.
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公开(公告)号：US20230195628A1
公开(公告)日：2023-06-22
申请号：US17558034
申请日：2021-12-21
IPC分类号： G06F12/0811 , G06F12/0853 , G06F13/16
CPC分类号： G06F12/0811 , G06F12/0853 , G06F13/1642 , G06F13/1668
摘要： Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.
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公开(公告)号：US20230032348A1
公开(公告)日：2023-02-02
申请号：US17956960
申请日：2022-09-30
IPC分类号： G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.
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公开(公告)号：US20220405209A1
公开(公告)日：2022-12-22
申请号：US17352628
申请日：2021-06-21
申请人： Intel Corporation
发明人： Kermin ChoFleming , Yu Bai , Ping Zou
IPC分类号： G06F12/0895 , G06F12/0853 , G06F12/0811 , G06F12/02
摘要： An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.
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公开(公告)号：US11461236B2
公开(公告)日：2022-10-04
申请号：US16882244
申请日：2020-05-22
IPC分类号： G06F12/08 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.
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公开(公告)号：US20220276965A1
公开(公告)日：2022-09-01
申请号：US17744810
申请日：2022-05-16
IPC分类号： G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.
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公开(公告)号：US11334494B2
公开(公告)日：2022-05-17
申请号：US16882387
申请日：2020-05-22
IPC分类号： G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.
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