公开(公告)号：US20230377989A1

公开(公告)日：2023-11-23

申请号：US18365832

申请日：2023-08-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC分类号： H01L21/8238 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L21/823814 ,  H01L29/45 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/0332 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/78618

摘要： A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US11824097B2

公开(公告)日：2023-11-21

申请号：US17667493

申请日：2022-02-08

申请人： Intel Corporation

发明人： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/4175 ,  H01L21/0262 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/32115 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6656

摘要： Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US11823959B2

公开(公告)日：2023-11-21

申请号：US17406276

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Chia-Hong Wu

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/28 ,  H01L29/45

CPC分类号： H01L21/823835 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/42364 ,  H01L29/517

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

公开(公告)号：US20230369102A1

公开(公告)日：2023-11-16

申请号：US18358707

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ta YU ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Yen-Chieh HUANG ,  Feng-Cheng YANG

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/532 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535

CPC分类号： H01L21/7682 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/45 ,  H01L23/5329 ,  H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535

摘要： A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

公开(公告)号：US20230369055A1

公开(公告)日：2023-11-16

申请号：US18359735

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L21/76814 ,  H01L21/02063 ,  H01L21/76895 ,  H01L21/31155 ,  H01L21/31111 ,  H01L21/76805

摘要： The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US11817486B2

公开(公告)日：2023-11-14

申请号：US18146435

申请日：2022-12-26

申请人： NXP USA, Inc.

发明人： James Albert Kirchgessner ,  Jay Paul John ,  Steven Kwan

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/737

CPC分类号： H01L29/42304 ,  H01L29/401 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7375

摘要： A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.

公开(公告)号：US20230363205A1

公开(公告)日：2023-11-09

申请号：US18351612

申请日：2023-07-13

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION ,  SONY GROUP CORPORATION

发明人： TAKASHI YAMAZAKI ,  KAZUHIRO TAMURA

IPC分类号： H10K59/121 ,  G09G3/3233 ,  H01L21/285 ,  H01L29/45 ,  H10K71/00

CPC分类号： H10K59/1213 ,  G09G3/3233 ,  H01L21/28518 ,  H01L29/456 ,  H10K71/00 ,  G09G2320/0233 ,  G09G2320/0238 ,  H10K59/1201

摘要： [Abstract] [Object] To provide a display device in which the occurrence of a bright spot defect is suppressed. [Solving Means] The display device includes a light-emitting portion and a drive circuit. The drive circuit includes a transistor that drives the light-emitting portion and includes a first diffusion layer and a first contact electrode, the first diffusion layer including no silicide formed in a silicon region, the first contact electrode being electrically connected to the first diffusion layer.

公开(公告)号：US11804554B2

公开(公告)日：2023-10-31

申请号：US17829749

申请日：2022-06-01

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Katsuhiko Fukasaku

IPC分类号： H01L29/06 ,  H01L29/868 ,  H01L29/165 ,  H01L29/36 ,  H01L29/45

CPC分类号： H01L29/868 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/36 ,  H01L29/45

摘要： A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.

公开(公告)号：US11804533B2

公开(公告)日：2023-10-31

申请号：US18173541

申请日：2023-02-23

申请人： Acorn Semi, LLC

发明人： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC分类号： H01L29/47 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283 ,  H01L29/45 ,  H01L21/324 ,  H01L29/161

CPC分类号： H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

摘要： Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

公开(公告)号：US11804528B2

公开(公告)日：2023-10-31

申请号：US17325466

申请日：2021-05-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sang Young Kim ,  Byung Chan Ryu ,  Da Un Jeon

IPC分类号： H01L29/417 ,  H01L23/522 ,  H01L29/45 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L29/786

CPC分类号： H01L29/41791 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/456 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78696

摘要： A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain pattern on the substrate, the source/drain pattern being at a side of the gate structure, a source/drain contact filling on and connected to the source/drain pattern, an entire top surface of the source/drain contact filling being lower than a top surface of the gate structure, and a connection contact directly on and connected to the source/drain contact filling, a top surface of the connection contact being higher than the top surface of the gate structure.