公开(公告)号：US09244067B2

公开(公告)日：2016-01-26

申请号：US13929654

申请日：2013-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Di Matteo ,  Vincenza Di Palma ,  Maria Fortuna Bevilacqua ,  Angela Cimmino

IPC: G01N33/543 ,  C12Q1/00

CPC classification number: G01N27/28 ,  C12Q1/001 ,  G01N27/327 ,  G01N27/403 ,  G01N33/54386 ,  G03F7/0035 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26

Abstract: A biosensor includes a flexible foil with an electrode layer positioned on the foil. An adhesive layer is positioned on the foil layer, and a first photo-definable hydrogel membrane is positioned over the electrode layer and the adhesive layer. A second photo-definable hydrogel membrane with an immobilized bio-recognition element is positioned over the first hydrogel membrane in contact with the electrode layer through an opening in the first hydrogel membrane.

Abstract translation: 生物传感器包括具有位于箔上的电极层的柔性箔。 粘合剂层位于箔层上，并且第一可光定影的水凝胶膜位于电极层和粘合剂层之上。 具有固定化生物识别元件的第二光可定义水凝胶膜通过第一水凝胶膜中的开口定位在与电极层接触的第一水凝胶膜的上方。

公开(公告)号：US09243967B2

公开(公告)日：2016-01-26

申请号：US13941893

申请日：2013-07-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giulio Ricotti ,  Juri Giovannone

IPC: G01L7/00 ,  G01L9/02 ,  G01L9/00 ,  G01L1/20 ,  G01L1/22 ,  D03D1/00 ,  H01C17/02 ,  A43B3/00 ,  A43D1/02 ,  D03D9/00 ,  D03D13/00 ,  D03D15/00 ,  A61B5/103 ,  A61B5/00

CPC classification number: G01L9/02 ,  A43B3/0005 ,  A43D1/025 ,  A61B5/1038 ,  A61B5/6807 ,  A61B2562/0247 ,  D03D1/0088 ,  D03D9/00 ,  D03D13/008 ,  D03D15/0094 ,  D10B2401/18 ,  G01L1/205 ,  G01L1/22 ,  G01L9/0002 ,  H01C17/02 ,  Y10T29/49087

Abstract: A sensor for pressure measurement may include a fabric support, an electrically conductive structure including tracks on the fabric support having resistance variations in response to deformations thereof, and a processor coupled to the electrically conductive structure and configured to sense resistance values of respective tracks of the electrically conductive structure and to provide a signal representative of a pressure difference across opposite faces of the fabric support.

Abstract translation: 用于压力测量的传感器可以包括织物支撑件，导电结构，其包括响应于其变形的电阻变化的织物支撑件上的轨道，以及耦合到导电结构并被配置为感测 并且提供表示在织物支撑体的相对面上的压力差的信号。

公开(公告)号：US20160011981A1

公开(公告)日：2016-01-14

申请号：US14664630

申请日：2015-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Paolo Rosingana ,  Marco Castellano

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G01D9/005 ,  G06F2212/1056 ,  G06F2212/451

Abstract: A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

Abstract translation: 多个传感器提供具有最高输出数据速率的第一传感器相应的输出数据速率，而一个或多个其它传感器具有作为上述最高输出数据速率的次数的输出数据速率。 来自传感器的数据信号通过将第一传感器的数据信号以上述最高输出数据速率存储在存储器（例如，FIFO存储器）中，伴随着来自所述第一传感器的数据信号的存储，存储 来自所述传感器的数据信号以所述其他传感器提供的上述多个输出数据速率，使得数据信号根据各种传感器共同的重复模式存储在存储器中。

公开(公告)号：US09237039B2

公开(公告)日：2016-01-12

申请号：US14307098

申请日：2014-06-17

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Salvatore Cassata ,  Francesco Pulvirenti ,  Salvatore Giuseppe Privitera

IPC: H03K3/00 ,  H04L25/02 ,  H04B3/00 ,  H02H9/04

CPC classification number: H04L25/0292 ,  H02H9/04 ,  H04B3/00 ,  H04L25/028 ,  Y10T29/49169

Abstract: A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.

Abstract translation: 收发器可连接至具有至少三根电线的电缆。 收发器可以包括受控的输出级，包括高侧支路，具有耦合在输出引脚和正电源引脚之间的具有串联耦合并具有公共电流端子的两个P型晶体管。 P型晶体管具有耦合到高侧支腿的公共电流端子的主体区域。 低侧支腿包括串联耦合并具有公共电流端子的两个N型晶体管，耦合在输出引脚和负电源引脚之间。 N型晶体管具有耦合到低侧支腿的公共电流端子的主体区域。 保护电路还包括耦合在公共电流端子之间的电压钳位器。

公开(公告)号：US09235300B2

公开(公告)日：2016-01-12

申请号：US13853870

申请日：2013-03-29

Applicant: STMicroelectronics Asia Pacific Pte. Ltd. ,  STMicroelectronics S.r.l.

Inventor： Paolo Angelini ,  Yannick Guedon ,  Ming Zi Zhu

IPC: G06G7/00 ,  G06F3/044 ,  G03G7/00 ,  G06F3/041

CPC classification number: G06F3/044 ,  G03G7/00 ,  G06F3/0418 ,  G06G7/00

Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.

Abstract translation: 用于完全或部分地从信号中去除噪声的累加器，包括消除蓄电池本身插入到信号中的噪声。 在一些实施例中，每当累加器对输入信号进行采样时，累加器可以在采样阶段和传送阶段中操作。 在一些这样的实施例中，累加器的累加电路的运算放大器可以在累积周期的某些或全部采样阶段期间自动归零。 在一些实施例中，在某些或所有采样相位期间运算放大器自动归零，其中累积电路可以包括保持电容器，其在自动归零过程期间保持由运算放大器输出的值 先前转移阶段。 在存储器中包括这种保持电容器可以降低运算放大器输出在自动归零过程之后上升的电压，这可以降低积累电路的带宽和噪声。

公开(公告)号：US09234911B2

公开(公告)日：2016-01-12

申请号：US14104873

申请日：2013-12-12

Applicant: STMicroelectronics S.r.l.

Inventor： Giuditta Roselli ,  Michele Tronconi ,  Fabio Pasolini

IPC: G01P13/00 ,  G06F13/24 ,  G06F1/16 ,  G06F3/01 ,  G06F3/038

CPC classification number: G01P15/125 ,  G01P13/00 ,  G01P15/0802 ,  G06F1/1613 ,  G06F1/1684 ,  G06F3/017 ,  G06F3/0383 ,  G06F13/24 ,  G06F2200/1636 ,  G06F2200/1637

Abstract: A sensor device for an electronic apparatus, including a sensing structure for generating a first detection signal, and a dedicated integrated circuit connected to the sensing structure for detecting a first event associated with the electronic apparatus and for generating a first interrupt signal upon detection of the first event. The dedicated integrated circuit detects the first event as a function of changes to the first detection signal over time (i.e., temporal evolution), and in particular as a function of values assumed by the first detection signal within one or more successive time windows, and of a relation between these values.

Abstract translation: 一种用于电子设备的传感器装置，包括用于产生第一检测信号的感测结构和连接到感测结构的专用集成电路，用于检测与电子设备相关联的第一事件，并且用于在检测到第一检测信号时产生第一中断信号 第一件事 专用集成电路根据一段时间内的第一检测信号（即，时间演化）检测第一事件，特别是作为第一检测信号在一个或多个连续时间窗内所假设的值的函数，以及 这些价值之间的关系。

公开(公告)号：US09231597B2

公开(公告)日：2016-01-05

申请号：US14261283

申请日：2014-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Calogero Marco Ippolito ,  Mario Chiricosta

IPC: H03L7/00 ,  H03L7/089

CPC classification number: H03L7/00 ,  H03L7/089

Abstract: A calibration circuit for a DCO includes a signal-conditioning module configured for (i) receiving at input an oscillating signal generated by the DCO and a reference signal, both designed to oscillate between a high logic value (“1”) and a low logic value (“0”), and (ii) detecting a respective first and second stable logic value of the reference signal and of the oscillating signal; and a period-to-voltage converter module coupled to the signal-conditioning module and configured for (iii) generating a difference signal identifying a difference between the period of the reference signal and the period of the oscillating signal, and (iv) controlling, on the basis of the difference signal, the DCO so as to conform the duration of the period of the oscillating signal to the duration of the period of the reference signal. Likewise described is a calibration method implemented by the calibration circuit.

Abstract translation: 用于DCO的校准电路包括信号调节模块，其被配置用于（i）在输入端接收由DCO产生的振荡信号和参考信号，两者被设计为在高逻辑值（“1”）和低逻辑 值（“0”），和（ii）检测参考信号和振荡信号的相应的第一和第二稳定逻辑值; 以及周期电压转换器模块，其耦合到所述信号调节模块并且被配置用于（iii）产生识别所述参考信号的周期与所述振荡信号的周期之间的差的差信号，以及（iv） 基于差分信号，DCO使得将振荡信号的周期的持续时间与参考信号的周期的持续时间相一致。 同样描述了由校准电路实现的校准方法。

公开(公告)号：US20150372075A1

公开(公告)日：2015-12-24

申请号：US14666013

申请日：2015-03-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Leonardo FRAGAPANE

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/0415 ,  H01L21/266 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611

Abstract: An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Abstract translation: 集成器件具有：掺杂有第一导电类型且具有限定平面的顶表面的半导体材料的结构层; 掺杂有第二导电类型的功能区域，其布置在所述结构层的顶表面的有源区域中，所述功能区域在所述集成器件的边缘区域附近，所述边缘区域在外部围绕所述有源区域; 并且掺杂有第二导电类型的边缘终止区域连接到功能区域并且布置在边缘区域中。 边缘终端区域具有在平行于平面的第一方向上变化的掺杂分布和结深度。

公开(公告)号：US09219481B2

公开(公告)日：2015-12-22

申请号：US14615915

申请日：2015-02-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mauro Scandiuzzo ,  Salvatore Valerio Cani ,  Claudio Mucci ,  Roberto Canegallo ,  Pier Luigi Rolandi

IPC: H03L5/00 ,  H03K19/0185 ,  H03K17/16

CPC classification number: H03K19/018507 ,  H03K17/16 ,  H03K19/018521 ,  Y10T29/49155

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

公开(公告)号：US20150364409A1

公开(公告)日：2015-12-17

申请号：US14733209

申请日：2015-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract translation: 电子装置包括集成在模具上的电路，其具有前表面和后表面，在前表面上具有模具端子。 模具嵌入包括具有前表面和后表面的导热材料的基底的包装和通孔中。 模具在通孔中沉没。 第一绝缘材料层用模具端子的第一窗口覆盖模具前表面和封装前表面。 封装端子和封装导轨布置在第一绝缘层上。 第二绝缘材料层覆盖第一绝缘层和封装轨道，其具有用于访问封装端子的第二窗口。