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公开(公告)号：US12133382B2
公开(公告)日：2024-10-29
申请号：US17678499
申请日：2022-02-23
发明人： Xiang Yin
IPC分类号： H10B41/27 , G11C16/04 , H01L23/522 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.
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公开(公告)号：US12132635B1
公开(公告)日：2024-10-29
申请号：US18353011
申请日：2023-07-14
摘要： Various embodiments include methods and systems for managing a volume of misbehavior reports. In various embodiments, a vehicle processing system may identify one or more misbehavior observations from among a plurality of misbehavior observations made by the vehicle processing system based on one or more volume management criteria for misbehavior report generation, generate a misbehavior report including information about the identified misbehavior observations, and transmit the generated misbehavior report to a network computing device.
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公开(公告)号：US12127406B2
公开(公告)日：2024-10-22
申请号：US17577533
申请日：2022-01-18
发明人： Takaaki Iwai , Takashi Inomata , Takayuki Maekura
IPC分类号： H01L25/18 , H01L23/00 , H01L23/535 , H01L25/00 , H01L25/065 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/00
CPC分类号： H10B43/27 , H01L23/535 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/35 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/34 , H10B63/845 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1441 , H01L2924/1444 , H01L2924/14511
摘要： A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
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4.发明授权公开(公告)号：US12125921B2
公开(公告)日：2024-10-22
申请号：US18354681
申请日：2023-07-19
发明人： Yong-Jie Wu , Hui-Hsien Wei , Yen-Chung Ho , Mauricio Manfrini , Chia-Jung Yu , Chung-Te Lin , Pin-Cheng Hsu
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/401 , H01L29/41733 , H01L29/41775 , H01L29/42364 , H01L29/42384 , H01L29/66742 , H01L29/78618 , H01L29/7869
摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
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公开(公告)号：US12124078B2
公开(公告)日：2024-10-22
申请号：US17548660
申请日：2021-12-13
发明人： Kuan-Yu Huang , Yu-Yun Huang , Tien-Yu Huang , Sung-Hui Huang , Sen-Bor Jan , Shang-Yun Hou
CPC分类号： G02B6/12002 , G02B6/124 , G02B6/13
摘要： A package assembly includes a package substrate including a first die that includes a photonic integrated circuit, a second die located on the first die, the second die including an electronic integrated circuit electrically connected to the photonic integrated circuit, and an interposer module on the package substrate, at least a portion of the interposer module being located on the first die and electrically connected to the photonic integrated circuit.
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公开(公告)号：US12109287B2
公开(公告)日：2024-10-08
申请号：US17878001
申请日：2022-07-31
申请人： L'Oreal
摘要： The disclosure relates to compositions for altering the color of keratin fibers and methods of using the compositions. The compositions comprise (a) a bonding system comprising (i) at least one first bonding agent chosen from lactic acid and/or salts thereof, and (ii) at least one second bonding agent chosen from amino acids and/or salts thereof; (b) at least one fatty alcohol; (c) at least one fatty acid; (d) at least one alkyl polyglucoside; (e) at least one alkalizing agent; and (f) at least one solvent. The compositions can further comprise one or more oxidation dyes, couplers, oxidizing agents, or combinations thereof.
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公开(公告)号：US12108597B2
公开(公告)日：2024-10-01
申请号：US17684975
申请日：2022-03-02
发明人： Teruo Okina , Shinsuke Yada , Ryo Yoshimoto
IPC分类号： H10B41/27 , G11C16/04 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H01L2224/06181 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541 , H01L2924/1431 , H01L2924/1451
摘要： A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.
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公开(公告)号：US12106790B2
公开(公告)日：2024-10-01
申请号：US17656306
申请日：2022-03-24
发明人： Alan Kalitsov , Derek Stewart , Ananth Kaushik , Gerardo Bertero
CPC分类号： G11C11/161 , G01R33/093 , G11C11/1673 , G11C11/1675 , H01F10/3286 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
摘要： A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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公开(公告)号：US12096632B2
公开(公告)日：2024-09-17
申请号：US17244311
申请日：2021-04-29
发明人： Koichi Matsuno , Johann Alsmeier
摘要： Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.
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10.发明授权公开(公告)号：US12094943B2
公开(公告)日：2024-09-17
申请号：US17587518
申请日：2022-01-28
发明人： Tomohiro Kubo , Yuki Kasai
IPC分类号： H01L21/00 , H01L21/28 , H01L29/423 , H10B43/27
CPC分类号： H01L29/4234 , H01L29/40117 , H10B43/27
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.
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