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1.发明申请公开(公告)号：US20160027869A1
公开(公告)日：2016-01-28
申请号：US14875176
申请日：2015-10-05
申请人： ADVANCED ANALOGIC TECHNOLOGIES (HONG KONG) LIMITED , ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
IPC分类号： H01L29/06 , H01L21/762 , H01L21/761
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.
摘要翻译： 形成在第一导电类型的半导体衬底中的隔离结构包括与第一导电类型相反的第二导电类型的区域。 第二导电类型的区域是碟形，并且具有基本上平行于基板的顶表面的底部部分和倾斜的侧壁部分。 倾斜的侧壁部分以斜角从基板的顶表面向下延伸并与底板部分合并。 地板部分和倾斜的侧壁部分一起形成基板的隔离袋。
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公开(公告)号：US20040251497A1
公开(公告)日：2004-12-16
申请号：US10767905
申请日：2004-01-28
IPC分类号： H01L029/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
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公开(公告)号：US20040119118A1
公开(公告)日：2004-06-24
申请号：US10423177
申请日：2003-04-24
IPC分类号： H01L023/62 , H01L021/66 , H01L021/8234
CPC分类号： H01L23/60 , H01L22/32 , H01L23/49562 , H01L23/62 , H01L24/05 , H01L24/48 , H01L24/49 , H01L27/0266 , H01L29/7802 , H01L29/7813 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05138 , H01L2224/05552 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48464 , H01L2224/49111 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S257/904 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.
摘要翻译： 半导体管芯具有用于诸如功率MOSFET的MOSFET的接合焊盘和用于ESD保护电路的单独的接合焊盘。 将焊盘连接在一起可使ESD保护电路起到保护MOSFET的作用。 在将焊盘连接在一起之前，ESD保护电路和/或MOSFET可以单独测试。 当测试MOSFET时，可以使用高于功能ESD保护电路的电压。 在倒装芯片封装中的引线接合或将管芯附接到衬底的封装工艺可以在测试之后连接焊盘。
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4.发明申请ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING TRENCHES CONTAINING CONDUCTIVE MATERIAL 有权半导体器件的隔离结构，包括导电材料的镀层公开(公告)号：US20160027868A1
公开(公告)日：2016-01-28
申请号：US14875165
申请日：2015-10-05
申请人： ADVANCED ANALOGIC TECHNOLOGIES (HONG KONG) LIMITED , ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
IPC分类号： H01L29/06
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： An isolation structure formed in a semiconductor substrate of a first conductivity type includes a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate. A first trench extends downward from a surface of the substrate and overlaps onto the floor isolation region. The first trench includes walls lined with a dielectric material and contains a conductive material. The first trench and the floor isolation region electrically isolate a pocket of the first conductivity type from the substrate.
摘要翻译： 形成在第一导电类型的半导体衬底中的隔离结构包括与浸没在衬底中的第一导电类型相反的第二导电类型的底部隔离区域。 第一沟槽从衬底的表面向下延伸并且重叠到地板隔离区域上。 第一沟槽包括内衬有电介质材料并包含导电材料的壁。 第一沟槽和底部隔离区域将第一导电类型的袋与衬底电隔离。
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5.发明授权Process for fabricating multi-die semiconductor package with one or more embedded die pads 有权用于制造具有一个或多个嵌入式管芯焊盘的多管芯半导体封装的工艺公开(公告)号：US08778740B2
公开(公告)日：2014-07-15
申请号：US13897423
申请日：2013-05-19
申请人： Advanced Analogic Technologies Incorporated , Advanced Analogic Technologies (Hong Kong) Limited
发明人： Richard K. Williams , Keng Hung Lin
CPC分类号： H01L25/50 , H01L23/49503 , H01L23/49551 , H01L23/49568 , H01L23/49575 , H01L24/48 , H01L24/85 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/10253 , H01L2924/12033 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. A process for fabricating the package includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad.
摘要翻译： 为了避免将多芯片半导体封装安装到印刷电路板（PCB）上的相邻裸片焊盘之间的短路，其中一个裸片焊盘嵌入聚合物胶囊中，而另一个芯片焊盘在封装的底部露出， 提供热释放通路到PCB。 当多芯片封装中的一个芯片产生比封装中的另一个裸片更多的热量时，这种布置是特别有用的。 用于制造封装的工艺包括限定嵌入式裸片焊盘的底表面的部分蚀刻，并且可以包括使整个连接到嵌入式裸片焊盘的触点或引线中的一个或多个的通蚀刻。
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6.发明申请Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology 有权模块化双极CMOS-DMOS模拟集成电路和功率晶体管技术公开(公告)号：US20040259318A1
公开(公告)日：2004-12-23
申请号：US10767680
申请日：2004-01-28
IPC分类号： H01L021/336 , H01L021/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
摘要翻译： 在不含外延层的基板中形成半导体器件系列。 在一个实施例中，该系列包括5V CMOS对，12V CMOS对，5V NPN，5V PNP，多种形式的横向沟槽MOSFET和30V侧向N沟道DMOS。 每个装置在横向和垂直方面非常紧凑，并且可以与基板中的所有其它装置完全隔离。
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