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1.发明申请Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology 有权模块化双极CMOS-DMOS模拟集成电路和功率晶体管技术公开(公告)号：US20040259318A1
公开(公告)日：2004-12-23
申请号：US10767680
申请日：2004-01-28
IPC分类号： H01L021/336 , H01L021/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
摘要翻译： 在不含外延层的基板中形成半导体器件系列。 在一个实施例中，该系列包括5V CMOS对，12V CMOS对，5V NPN，5V PNP，多种形式的横向沟槽MOSFET和30V侧向N沟道DMOS。 每个装置在横向和垂直方面非常紧凑，并且可以与基板中的所有其它装置完全隔离。
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公开(公告)号：US20040119118A1
公开(公告)日：2004-06-24
申请号：US10423177
申请日：2003-04-24
IPC分类号： H01L023/62 , H01L021/66 , H01L021/8234
CPC分类号： H01L23/60 , H01L22/32 , H01L23/49562 , H01L23/62 , H01L24/05 , H01L24/48 , H01L24/49 , H01L27/0266 , H01L29/7802 , H01L29/7813 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05138 , H01L2224/05552 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48464 , H01L2224/49111 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S257/904 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.
摘要翻译： 半导体管芯具有用于诸如功率MOSFET的MOSFET的接合焊盘和用于ESD保护电路的单独的接合焊盘。 将焊盘连接在一起可使ESD保护电路起到保护MOSFET的作用。 在将焊盘连接在一起之前，ESD保护电路和/或MOSFET可以单独测试。 当测试MOSFET时，可以使用高于功能ESD保护电路的电压。 在倒装芯片封装中的引线接合或将管芯附接到衬底的封装工艺可以在测试之后连接焊盘。
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公开(公告)号：US20040251497A1
公开(公告)日：2004-12-16
申请号：US10767905
申请日：2004-01-28
IPC分类号： H01L029/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
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公开(公告)号：US20040173844A1
公开(公告)日：2004-09-09
申请号：US10383231
申请日：2003-03-05
IPC分类号： H01L029/76
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66734 , H01L29/7811
摘要： Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
摘要翻译： 功率MOSFET的功率MOSFET和制造工艺在沟槽内使用连续的导电栅极结构，以避免当栅极总线延伸到衬底表面之上时引起的器件拓扑引起的问题。 导电栅极结构在有源器件区域中的器件沟槽中形成栅极，并在栅极总线沟槽中形成栅极总线。 连接到器件沟槽的栅极总线沟槽可以是宽的，以便于与栅极总线形成栅极接触，而器件沟槽可以窄以使器件密度最大化。 可以使用CMP工艺来平坦化导电栅极结构和/或覆盖绝缘层。 该过程与在有源器件区域中形成自对准或常规触点的工艺兼容。
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