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    Multi-channel broadband content distribution system
    1.
    发明申请
    Multi-channel broadband content distribution system 有权
    多通道宽带内容分发系统

    公开(公告)号：US20030083054A1

    公开(公告)日：2003-05-01

    申请号：US10172777

    申请日：2002-06-14

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Anthony Francesca ,  WeiMin Zhang

    IPC: H04M003/00

    CPC classification number: H04L5/0005 ,  H04L5/0064 ,  H04L5/06 ,  H04L67/32 ,  H04L67/34 ,  H04L69/14 ,  H04N21/23412 ,  H04N21/2365 ,  H04N21/2383 ,  H04N21/2385 ,  H04N21/2402

    Abstract: A system for managing bandwidth in a content distribution system is provided. The system can be incorporated into the content head end of the content distribution system. The system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. How the packets are multiplexed by the program multiplexer into the output queue depends on the specific design and/or application. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal. The frequency block-up converter then takes the analog multi-channel RF signal and shifts its to a higher frequency band for transmission. The shifted analog multi-channel RF signal is then transmitted over a medium to one or more customer premises equipment.

    Abstract translation: 提供了一种用于管理内容分发系统中的带宽的系统。 该系统可以并入到内容分发系统的内容头端。 该系统包括程序多路复用器，多通道调制模块，通道多路复用器，数模转换器和频率块转换器，全部以顺序配置排列。 表示各个内容节目的分组被馈送到节目多路复用器。 程序复用器将数据包复用到输出队列中。 数据包如何被程序多路复用器复用到输出队列中取决于具体的设计和/或应用程序。 然后将来自输出队列的数据包送入多通道调制模块。 多通道调制模块接收分组并将它们路由到表示对应RF信道的各种调制器。 然后，各种调制器调制各个分组以产生对应的RF信号。 然后，这些RF信号被信道多路复用器复用成多信道RF信号。 然后将多通道RF信号转发到数模转换器，以转换成模拟多通道RF信号。 然后，频率块转换器接收模拟多声道RF信号并将其移动到较高频带以进行传输。 然后将移位的模拟多声道RF信号通过介质传送到一个或多个客户驻地设备。

    High Throughput Interleaver/De-Interleaver
    2.
    发明申请
    High Throughput Interleaver/De-Interleaver 有权
    高吞吐量交织器/去交织器

    公开(公告)号：US20130212328A1

    公开(公告)日：2013-08-15

    申请号：US13725109

    申请日：2012-12-21

    Applicant: BroadLogic Network Technologies Inc.

    Inventor： Binfan Liu ,  Junyi Xu

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

    Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

    Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/去交织器对通过隐藏有效和预充电周期而突发定向的DDR SDRAM执行读取和写入访问，以便实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

    Error correction coding across multiple channels in content distribution systems
    3.
    发明申请
    Error correction coding across multiple channels in content distribution systems 有权
    内容分发系统中多个通道的纠错编码

    公开(公告)号：US20030167432A1

    公开(公告)日：2003-09-04

    申请号：US10087202

    申请日：2002-03-01

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Wei-Min Zhang ,  Timothy A. Misko

    IPC: H04L001/00 ,  G06F011/00

    CPC classification number: H03M13/29 ,  H03M13/2978 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0076 ,  H04L25/14

    Abstract: Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of redundancy data, including the portion of redundancy data in at least one redundancy channel, and transmitting the redundancy channel along with the original channels. Error correction is achieved by receiving at least one redundancy channel and a plurality of original channels, selecting a portion of redundancy data from the redundancy channel, selecting a portion of original data from each of the original channels, and performing at least one decoding operation using the portion of redundancy data and the portions of original data to correct at least one error in the portions of original data.

    Abstract translation: 在多信道传输系统中提供了跨多个信道的纠错编码。 具体地，通过从多个原始信道中的每一个选择一部分原始数据来提供冗余，使用原始数据的部分执行至少一个编码操作，以产生冗余数据的至少一部分，包括冗余数据的一部分 至少一个冗余信道，并且与原始信道一起发送冗余信道。 通过接收至少一个冗余信道和多个原始信道，从冗余信道中选择冗余数据的一部分，从每个原始信道中选择一部分原始数据，并使用 冗余数据的部分和原始数据的部分以校正原始数据的部分中的至少一个错误。

    Multi-stream access scheme for high speed access and recording using a hard disk drive
    4.
    发明申请
    Multi-stream access scheme for high speed access and recording using a hard disk drive 有权
    使用硬盘驱动器进行高速访问和记录的多流访问方案

    公开(公告)号：US20030131191A1

    公开(公告)日：2003-07-10

    申请号：US10305260

    申请日：2002-11-25

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Weimin Zhang ,  Tony Francesca

    IPC: G06F012/00

    CPC classification number: G11B20/10 ,  G11B2020/1074

    Abstract: A system for facilitating high-speed access and recording is provided. The system includes a demodulator, an buffer memory and a hard disk. During a write cycle, the demodulator is used to receive one or more content streams. The content streams received by the demodulator are first stored in the buffer memory. When the buffer memory has reached its storage capacity, its contents are then transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. Other components of the system can then access the read-out contents from the buffer memory. The amount of contents retrieved from the hard disk and stored in the buffer memory may be more than what is requested depending on the application requesting the contents. The hard disk further includes different zones. There are two types of zones, namely, high-speed zone and random-access zone. The two different types of zones allow for a number of operating modes, namely, the high-speed mode, the random-access mode and the buffer-cleaning mode. In the high-speed mode, contents from the buffer memory are transferred to the high-speed zone in a continuous manner regardless of the nature or classification of the contents. In the random-access mode, contents from the buffer memory are respectively transferred to the appropriate locations in the random-access zone based on the nature or classification of the contents. In the buffer-cleaning mode, contents stored in the high-speed zone are transferred to appropriate locations in the random-access zone based on the nature or classification of the contents.

    Abstract translation: 提供了一种便于高速访问和记录的系统。 该系统包括解调器，缓冲存储器和硬盘。 在写周期期间，解调器用于接收一个或多个内容流。 由解调器接收的内容流首先存储在缓冲存储器中。 当缓冲存储器达到其存储容量时，其内容将被传送到硬盘进行存储。 在读取周期中，读取硬盘中的内容，然后存储在缓冲存储器中。 然后，系统的其他组件可以从缓冲存储器访问读出的内容。 根据请求内容的应用程序，从硬盘检索并存储在缓冲存储器中的内容量可能大于请求的内容。 硬盘还包括不同的区域。 有两种类型的区域，即高速区和随机接入区。 两种不同类型的区域允许多种操作模式，即高速模式，随机访问模式和缓冲清理模式。 在高速模式中，无论内容的性质或分类如何，来自缓冲存储器的内容都以连续的方式被传送到高速区。 在随机访问模式中，根据内容的性质或分类，将来自缓冲存储器的内容分别传送到随机访问区域中的适当位置。 在缓冲清理模式中，基于内容的性质或分类，将存储在高速区中的内容传送到随机存取区中的适当位置。

    Multi-Reference Clock Synchronization Techniques
    6.
    发明申请
    Multi-Reference Clock Synchronization Techniques 有权
    多参考时钟同步技术

    公开(公告)号：US20130156117A1

    公开(公告)日：2013-06-20

    申请号：US13767625

    申请日：2013-02-14

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Binfan Liu ,  Junyi Xu ,  Weimin Zhang

    IPC: H04L7/00

    CPC classification number: H04L7/0037 ,  H03L7/06 ,  H04J3/0638 ,  H04J3/0658 ,  H04L27/36

    Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

    Abstract translation: 在EQAM设备中支持多个参考时钟的高效同步技术。 考虑在EQAM设备中接收来自具有对应的不同定时参考（即，不同的源参考时钟）的相应多个不同源的数据的多个不同调制器。 为了适应这一点，调制器都使用公共系统时钟进行操作，并且每个调制器都配备有相位同步器。 相位同步器将调制的符号相位同步到相应的参考时钟。

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