公开(公告)号：US06545350B2

公开(公告)日：2003-04-08

申请号：US09774789

申请日：2001-01-31

Applicant: Kai-Kuang Ho ,  Te-Sheng Yang ,  Charlie Han

Inventor： Kai-Kuang Ho ,  Te-Sheng Yang ,  Charlie Han

IPC: H01L2310

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

公开(公告)号：US06399421B2

公开(公告)日：2002-06-04

申请号：US09797546

申请日：2001-03-01

Applicant: Charlie Han ,  Te-Sheng Yang

Inventor： Charlie Han ,  Te-Sheng Yang

IPC: H01L2144

CPC classification number: H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Abstract translation: 提供了双模封装结构。 双模封装结构包括引线框架，引线框架还包括管芯焊盘和多个引脚，其中管芯焊盘包括上表面和下表面。 具有多个第一接合焊盘的第一管芯通过例如胶合而固定在管芯焊盘的上表面上。 第一个焊盘保持暴露。 具有多个第二接合焊盘的第二管芯通过例如胶合而固定在下表面上。 第二个焊盘保持暴露。 凸起再分配结构层位于第二管芯上，以将每个第二接合焊盘重新分布到伪接合焊盘。 每个伪焊盘相对于第一焊盘具有适当的位置。 因此，当使用多个接合线将第一接合焊盘和伪接合焊盘接合到引线脚时，可以规则地且简单地接合接合线而不会彼此交叉或缠结。

公开(公告)号：US06352923B1

公开(公告)日：2002-03-05

申请号：US09260219

申请日：1999-03-01

Applicant: Min-Chih Hsuan ,  Charlie Han

Inventor： Min-Chih Hsuan ,  Charlie Han

IPC: H01L2144

CPC classification number: H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05085 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/16 ,  H01L2224/48137 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/05124 ,  H01L2224/05147

Abstract: A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Abstract translation: 一种制造直接接触通孔型晶片的方法。 器件和接触插塞形成在绝缘体上硅衬底的一侧，多层互连形成在绝缘体上硅衬底的侧面上。 多层互连与设备和接触插头耦合。 与多层互连耦合的接合焊盘在多层互连上形成。 在绝缘体上硅衬底的另一侧上形成开口以露出接触插塞。 在开口中依次形成绝缘层，阻挡层和金属层。 分别在接合焊盘和金属层上形成凸起。

公开(公告)号：US06313527B1

公开(公告)日：2001-11-06

申请号：US09210270

申请日：1998-12-10

Applicant: Charlie Han ,  Te-Sheng Yang

Inventor： Charlie Han ,  Te-Sheng Yang

IPC: H01L2334

CPC classification number: H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Abstract translation: 提供了双模封装结构。 双模封装结构包括引线框架，引线框架还包括管芯焊盘和多个引脚，其中管芯焊盘包括上表面和下表面。 具有多个第一接合焊盘的第一管芯通过例如胶合而固定在管芯焊盘的上表面上。 第一个焊盘保持暴露。 具有多个第二接合焊盘的第二管芯通过例如胶合而固定在下表面上。 第二个焊盘保持暴露。 凸起再分配结构层位于第二管芯上，以将每个第二接合焊盘重新分布到伪接合焊盘。 每个伪焊盘相对于第一焊盘具有适当的位置。 因此，当使用多个接合线将第一接合焊盘和伪接合焊盘接合到引线脚时，可以规则地且简单地接合接合线而不会彼此交叉或缠结。

公开(公告)号：US06820029B2

公开(公告)日：2004-11-16

申请号：US09742224

申请日：2000-12-22

Applicant: Walx Fang ,  Charlie Han

Inventor： Walx Fang ,  Charlie Han

IPC: H01L2166

CPC classification number: G01R31/30

Abstract: A method for determining failure rate and selecting a best burn-in time is disclosed. The method comprises the following steps. First of all, integrate circuits are provided. Then a life-time testing process is performed, wherein a failure rate versus testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, wherein an acceleration factor function also is established under the testing environment. Next a simulating process that uses a testing time function is performed to simulate the failure rate versus testing time relation. Then a transforming process that uses the acceleration factor function is performed to transform the testing time function into a real time function. Finally, an integrating process is performed to integrate the real time function through a calculating region to acquire an accumulated failure rate real time function.

Abstract translation: 公开了一种确定故障率并选择最佳老化时间的方法。 该方法包括以下步骤。 首先提供集成电路。 然后进行终身测试过程，其中通过测量测试环境下的每个集成电路的寿命来建立故障率与测试时间关系，其中在测试环境下也建立加速因子函数。 接下来，使用使用测试时间功能的模拟过程来模拟故障率与测试时间关系。 然后执行使用加速因子函数的变换过程，以将测试时间函数转换为实时函数。 最后，进行积分处理，通过计算区域对实时功能进行积分，以获取累积的故障率实时功能。

公开(公告)号：US06669520B2

公开(公告)日：2003-12-30

申请号：US09682550

申请日：2001-09-19

Applicant: Chin-Lung Hung ,  Charlie Han ,  Wei-Hsiao Chen

Inventor： Chin-Lung Hung ,  Charlie Han ,  Wei-Hsiao Chen

IPC: H01J924

CPC classification number: G02F1/13394

Abstract: A backplane with multiple arrayed electrodes positioned on the backplane is provided in a method of fabricating a liquid crystal (LC) panel. The method begins with coating an alignment layer on the backplane. By performing a rubbing process, multiple alignment trenches are formed on the alignment layer. A photoresist layer is then formed on the alignment layer. By performing a lithography process, both a side frame, having at least one slit, and multiple photoresist spacers(PR spacers) are formed on the alignment layer. A gasket seal is coated on the side frame and the multiple PR spacers. By performing a lamination process, a transparent conductive layer is laminated on the backplane. A liquid crystal filling (LC filling) processis then performed to fill a cell gap between the backplane and the transparent conductive layer with liquid crystal. Finally, an end sealing process is performed to seal the slit.

Abstract translation: 在制造液晶（LC）面板的方法中提供了设置在背板上的多个阵列电极的背板。 该方法开始于在背板上涂覆取向层。 通过进行摩擦处理，在取向层上形成多个取向沟。 然后在对准层上形成光致抗蚀剂层。 通过进行光刻处理，在取向层上形成具有至少一个狭缝的侧框架和多个光刻胶间隔物（PR间隔物）。 垫片密封件涂覆在侧框架和多个PR垫片上。 通过进行层压处理，在背板上层叠透明导电层。 然后进行液晶填充（LC填充）处理以用液晶填充背板和透明导电层之间的单元间隙。 最后，进行封口处理以密封狭缝。

公开(公告)号：US06512708B1

公开(公告)日：2003-01-28

申请号：US09981650

申请日：2001-10-16

Applicant: Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

Inventor： Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

IPC: G11V700

CPC classification number: H01L22/22 ,  G06F17/5068 ,  G11C11/4097 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals. During fabrication, the replacement of defective chips with spare chips is accomplished by using two extra conductive layers and patterning the extra layers using a mask that is independent of the defect distribution of a particular wafer.

Abstract translation: 用于晶片刻度存储器和放置方法的架构用存储器模块中的备用芯片代替有缺陷的芯片，以便提供最小临界信号延迟。 SDRAM存储器芯片被分为正常芯片和备用芯片，其中普通芯片形成为诸如行或列的组，并且备用芯片用于替换有缺陷的普通芯片。 金属线和通孔的延迟模型用于计算放置和布线的信号延迟。 放置问题被建模为二分图，并使用分支和约束算法来求解具有最短关键信号延迟的芯片替换配置。 还描述了分级路由方法，其将信号分类成不同类型和级别的信号。 在制造期间，通过使用两个额外的导电层并且使用独立于特定晶片的缺陷分布的掩模对附加层进行图案化来实现用备用芯片替换有缺陷的芯片。

公开(公告)号：US06323546B2

公开(公告)日：2001-11-27

申请号：US09753735

申请日：2001-01-02

Applicant: Min Chih Hsuan ,  Charlie Han

Inventor： Min Chih Hsuan ,  Charlie Han

IPC: H01L2302

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05085 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

公开(公告)号：US6133629A

公开(公告)日：2000-10-17

申请号：US299681

申请日：1999-04-26

Applicant: Charlie Han ,  Ming-Huang Hung

Inventor： Charlie Han ,  Ming-Huang Hung

IPC: H01L21/66 ,  H01L21/98 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538 ,  H01L23/04

CPC classification number: H01L24/32 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/5382 ,  H01L24/98 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A repairable multi-chip module which is used when failures are found after an electrically and functionally testing is described. A substrate is provided. At least a first normal die having a plurality of first pads is mounted on the substrate, wherein the first normal die is surrounded by the pads. At least a failed die is mounted on the substrate. Several third pads and fourth pads are mounted on the substrate, wherein the third pads surrounds the first normal die and the failed die and the fourth pads surrounds the first pads. At least a second normal die having a plurality of second pads is stacked over the failed die. Several conductive wires are electrically connecting the first pads on the first normal die and the third pads. Several reworking conductive wires are electrically connecting the second pads on the second normal die and the fourth pads.

Abstract translation: 描述了在电气和功能测试之后发现故障时使用的可修复的多芯片模块。 提供基板。 至少具有多个第一焊盘的第一正常裸片安装在衬底上，其中第一正常裸片被焊盘包围。 至少一个失效的模具安装在基板上。 几个第三焊盘和第四焊盘安装在衬底上，其中第三焊盘包围第一正常裸片和失效裸片，第四焊盘围绕第一焊盘。 具有多个第二焊盘的至少第二正常裸片堆叠在失效的裸片上。 几条导线电连接第一正常裸片上的第一焊盘和第三焊盘。 几个返工导线电连接第二正常裸片上的第二焊盘和第四焊盘。

公开(公告)号：US5995428A

公开(公告)日：1999-11-30

申请号：US32627

申请日：1998-02-27

Applicant: Pien Chien ,  Shih-Chin Lin ,  Charlie Han

Inventor： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC: G01R31/28 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50 ,  G01R31/2856 ,  G11C11/401

Abstract: A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

Abstract translation: 提供了一种电路，用于在形成有多个骰子的晶片上使用，每个骰子具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过该电路，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。