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    Placement and routing for wafer scale memory
    2.
    发明授权
    Placement and routing for wafer scale memory 失效
    硅片刻度存储器的放置和布线

    公开(公告)号：US06512708B1

    公开(公告)日：2003-01-28

    申请号：US09981650

    申请日：2001-10-16

    Applicant: Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

    Inventor： Min-Chih Hsuan ,  Tazsheng Feng ,  Charlie Han ,  Cheng-ju Hsieh

    IPC: G11V700

    CPC classification number: H01L22/22 ,  G06F17/5068 ,  G11C11/4097 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals. During fabrication, the replacement of defective chips with spare chips is accomplished by using two extra conductive layers and patterning the extra layers using a mask that is independent of the defect distribution of a particular wafer.

    Abstract translation: 用于晶片刻度存储器和放置方法的架构用存储器模块中的备用芯片代替有缺陷的芯片，以便提供最小临界信号延迟。 SDRAM存储器芯片被分为正常芯片和备用芯片，其中普通芯片形成为诸如行或列的组，并且备用芯片用于替换有缺陷的普通芯片。 金属线和通孔的延迟模型用于计算放置和布线的信号延迟。 放置问题被建模为二分图，并使用分支和约束算法来求解具有最短关键信号延迟的芯片替换配置。 还描述了分级路由方法，其将信号分类成不同类型和级别的信号。 在制造期间，通过使用两个额外的导电层并且使用独立于特定晶片的缺陷分布的掩模对附加层进行图案化来实现用备用芯片替换有缺陷的芯片。

    Cascade-type chip module
    5.
    发明授权
    Cascade-type chip module 有权
    级联型芯片模块

    公开(公告)号：US6166444A

    公开(公告)日：2000-12-26

    申请号：US337708

    申请日：1999-06-21

    Applicant: Min-Chih Hsuan ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Charlie Han

    IPC: H01L25/065 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L29/40

    CPC classification number: H01L25/0652 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/013

    Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group. The chips are coupled to each other by bumps. The chips are attached to the laminate substrate and the first group and the second group are respectively coupled with the contacts by two film carriers.

    Abstract translation: 级联型芯片模块。 提供具有触点的层叠基板。 提供了适用于级联型模块的芯片。 每个芯片包括具有第一区域和第二区域的再分配层，并且凸块接触再分布层上方。 与再分布层的第一区域耦合的突起触点的布局是与再分布层的第二区域耦合的布局的布局旋转对称的图像，并且与第一区域耦合的每个凸起触点与 通过再分布层与第二区域相应的凸起接触。 芯片分为第一组和第二组; 第一组堆叠在第二组上，使得第一组的每个芯片的第一区域与第二组的每个芯片的第二区域对准，并且第一组的每个芯片的第二区域与第一组的第一组对准 第二组的每个芯片的区域。 芯片通过凸块相互耦合。 芯片附接到层叠基板，第一组和第二组分别通过两个薄膜载体与触点耦合。

    Preburn-in dynamic random access memory module and preburn-in circuit board thereof
    7.
    发明授权
    Preburn-in dynamic random access memory module and preburn-in circuit board thereof 失效
    Preburn-in动态随机存取存储器模块及其Preburn-in电路板

    公开(公告)号：US06279141B1

    公开(公告)日：2001-08-21

    申请号：US09434987

    申请日：1997-08-13

    Applicant: Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    Inventor： Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    IPC: G06F1750

    CPC classification number: G11C29/56016 ,  G11C11/401 ,  G11C29/48 ,  H05K1/0286 ,  H05K3/0052

    Abstract: A preburn-in DRAM module circuit board is provided, which allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked. After the burn-in process, each of the DRAM modules can be cut apart from the circuit board to serve as a single memory module. The preburn-in DRAM module circuit board allows the manufacturing process for the DRAM modules to be reduced in schedule and manufacturing cost. Material cost can also be saved since the burn-in circuit and the module circuit are arranged on the same circuit board.

    Abstract translation: 提供了一种预烧入式DRAM模块电路板，其允许在其上直接构建多个DRAM模块，并且其可以直接连接到大型老化炉，以便在DRAM上同时执行老化过程 安装在其上的模块，以检查要重新加工的任何缺陷的IC芯片。 在老化过程之后，可以将每个DRAM模块与电路板分开以用作单个存储器模块。 预烧入式DRAM模块电路板允许在时间表和制造成本上减少DRAM模块的制造过程。 由于老化电路和模块电路布置在同一电路板上，因此也可节省材料成本。

    Wafer level integrated circuit structure and method of manufacturing the same
    8.
    发明授权
    Wafer level integrated circuit structure and method of manufacturing the same 有权
    晶圆级集成电路结构及其制造方法

    公开(公告)号：US06214630B1

    公开(公告)日：2001-04-10

    申请号：US09471059

    申请日：1999-12-22

    Applicant: Min-Chih Hsuan ,  Taisheng Feng ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Taisheng Feng ,  Charlie Han

    IPC: H01L2100

    CPC classification number: H01L22/22 ,  G01R31/318505 ,  G01R31/318511 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use. The overall IC manufacture would have an increased yield as compared to the prior art.

    Abstract translation: 提出了晶片级IC结构和制造该晶片级IC结构的方法，这有助于提高IC制造的成品率。 晶片级IC结构构造在半导体晶片上，半导体晶片被限定在晶片上的多个分立IC块中，每个IC块用于形成诸如存储单元的多个IC部件。 形成多层互连结构以将每个IC块中的这些IC部件电连接。 然后执行第一个测试和修复过程，以断开任何不起作用的IC组件的主动使用。 这完成了制造过程的制造阶段。 在随后的封装阶段中，形成再分配线结构以将分立IC块互连成为一体的功能单元。 然后执行第二个测试和修复过程以断开任何不工作的IC块与主动使用。 与现有技术相比，整体IC制造将具有增加的产量。

    Repairable memory module and method of repairing memory modules
    9.
    发明授权
    Repairable memory module and method of repairing memory modules 失效
    可修复的内存模块和修复内存模块的方法

    公开(公告)号：US5875136A

    公开(公告)日：1999-02-23

    申请号：US907642

    申请日：1997-08-11

    Applicant: Min-Chih Hsuan ,  Jerry Jaw ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Jerry Jaw ,  Charlie Han

    IPC: G11C5/06

    CPC classification number: G11C29/81 ,  G11C29/808 ,  G11C29/816 ,  G11C5/04

    Abstract: A repairable memory module, such as a DRAM (dynamic random access memory) or a flash memory module, and a method of repairing memory modules are proposed. Based on the repairable memory module, any failed memory ICs in the module that are found before shipment or after use can be repaired through the use of a backup memory IC. Fundamentally, when any failed memory ICs are found in the module, a set of zero-ohm resistors are used to short-circuit a number of selected pairs of jumping pads to thereby redirect the connections to the I/O (input/output) and column-address strobe pins on the failed memory IC instead to the same nominal pins on the backup memory IC. This allows the function of the failed ICs to be instead performed by the backup memory chip.

    Abstract translation: 提出了诸如DRAM（动态随机存取存储器）或闪速存储器模块的可修复存储器模块以及修复存储器模块的方法。 基于可修复的存储器模块，可以通过使用备用存储器IC来修复在发货之前或使用后发现的模块中的任何故障存储器IC。 基本上，当在模块中发现任何失败的存储器IC时，使用一组零欧姆电阻器来使多个选定跳跃焊盘对短路，从而将连接重定向到I / O（输入/输出）和 故障存储器IC上的列地址选通引脚替代为备用存储器IC上的相同标称引脚。 这允许由备用存储器芯片替代执行故障IC的功能。

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