公开(公告)号：US10242942B2

公开(公告)日：2019-03-26

申请号：US15127708

申请日：2014-04-25

申请人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

发明人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US07321172B2

公开(公告)日：2008-01-22

申请号：US11227532

申请日：2005-09-14

申请人： Dustin P. Wood ,  Debendra Mallik

发明人： Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US07186645B2

公开(公告)日：2007-03-06

申请号：US10685171

申请日：2003-10-13

申请人： Dustin P. Wood ,  Debendra Mallik

发明人： Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L21/44

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US09530758B2

公开(公告)日：2016-12-27

申请号：US14750811

申请日：2015-06-25

申请人： Debendra Mallik ,  Robert L. Sankman

发明人： Debendra Mallik ,  Robert L. Sankman

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01079 ,  H01L2224/11

摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

公开(公告)号：US20150294958A1

公开(公告)日：2015-10-15

申请号：US14750811

申请日：2015-06-25

申请人： Debendra Mallik ,  Robert L. Sankman

发明人： Debendra Mallik ,  Robert L. Sankman

IPC分类号： H01L25/065 ,  H01L21/304 ,  H01L21/82 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01079 ,  H01L2224/11

摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

摘要翻译： 描述了具有通过模具一级互连的3D集成电路封装以及形成这种封装的方法。 例如，半导体封装包括衬底。 底部半导体管芯具有表面积的活性侧。 底部半导体管芯与主体侧远离衬底耦合到衬底。 顶部半导体管芯具有活性侧，其表面积大于底部半导体管芯的表面积。 顶部半导体管芯耦合到衬底，其中有源侧靠近衬底。 底部半导体管芯的有源侧面向并导电耦合到顶部半导体管芯的有源侧。 顶部半导体管芯通过旁路底部半导体管芯的一级互连导体耦合到衬底。

公开(公告)号：US09136236B2

公开(公告)日：2015-09-15

申请号：US13630297

申请日：2012-09-28

申请人： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

发明人： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC分类号： H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

摘要： Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

摘要翻译： 本文通常描述用于局部高密度衬底布线的系统和方法的实施例。 在一个或多个实施例中，一种装置包括介质，第一和第二电路元件，互连元件和电介质层。 该介质可以包括其中的低密度路由。 互连元件可以嵌入在介质中，并且可以在其中包括多个导电构件，导电构件可以电耦合到第一电路元件和第二电路元件。 互连元件可以包括其中的高密度路由。 电介质层可以在互连裸片上方，电介质层包括通过其中的第一和第二电路元件。

公开(公告)号：US20140029639A1

公开(公告)日：2014-01-30

申请号：US13976419

申请日：2011-12-28

申请人： Edward A. Zarbock ,  Debendra Mallik

发明人： Edward A. Zarbock ,  Debendra Mallik

IPC分类号： H01S5/00

CPC分类号： G02B6/4214 ,  G02B6/4206 ,  G02B6/4238 ,  G02B6/4249 ,  G02B6/4269 ,  G02B6/4274 ,  H01L25/167 ,  H01L2924/0002 ,  H01S5/0071 ,  H01S5/021 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02469 ,  H01S5/0261 ,  H01L2924/00

摘要： A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.

摘要翻译： 光子封装包括在裸片前侧具有光子发射器的光子器件。 来自光子发射器的光束从模具的前侧延伸到背面，穿过基本上对于光子束透明的管芯的衬底材料到管芯的背面。 还描述了其它实施例。

公开(公告)号：US20120153495A1

公开(公告)日：2012-06-21

申请号：US12973596

申请日：2010-12-20

申请人： Debendra Mallik ,  Mihir K. Roy

发明人： Debendra Mallik ,  Mihir K. Roy

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/16225 ,  H05K1/113 ,  H05K1/115

摘要： Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

摘要翻译： 实施例涉及具有减小尺寸的电镀通孔（PTH）焊盘的半导体封装，通过消除焊盘到PTH对准的边缘并且使得能够在衬底的芯上更细的迹线。

公开(公告)号：US20090079061A1

公开(公告)日：2009-03-26

申请号：US12277109

申请日：2008-11-24

申请人： Debendra Mallik ,  Robert L. Sankman

发明人： Debendra Mallik ,  Robert L. Sankman

IPC分类号： H01L23/36

CPC分类号： H05K1/0204 ,  H01L23/13 ,  H01L23/36 ,  H01L23/4006 ,  H01L23/49816 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/1056 ,  H05K2201/10734 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One or more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.

摘要翻译： 一种用于制造具有改善的热传导特性和高频响应的封装的方法和装置。 诸如铜的相对厚的封装衬底具有结合到一个面的布线层，使相对的面露出，例如是用于连接到散热器的表面。 将一个或多个芯片接合到布线层，并且在芯片的周边周围设置连接器阵列（例如焊球），以连接到印刷电路板。 在一些实施例中，印刷电路板具有一个孔，芯片延伸进入以允许更小的外部连接焊球。 在一些实施例中，第二散热器通过PCB孔连接到芯片的背面。

公开(公告)号：US07345361B2

公开(公告)日：2008-03-18

申请号：US10728324

申请日：2003-12-04

申请人： Debendra Mallik ,  Kinya Ichikawa ,  Terry L. Sterrett ,  Johanna Swan

发明人： Debendra Mallik ,  Kinya Ichikawa ,  Terry L. Sterrett ,  Johanna Swan

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

摘要翻译： 系统可以包括集成电路管芯，耦合到集成电路管芯的集成电路封装，与集成电路管芯接触的模具化合物和集成电路封装以及耦合到集成电路封装的互连。 互连的第一部分可以与模具化合物接触，互连的第二部分可能不接触模具化合物，并且互连的第三部分可以与集成电路封装接触。