公开(公告)号：US20120049385A1

公开(公告)日：2012-03-01

申请号：US13289365

申请日：2011-11-04

Applicant: Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract translation: 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US20080318361A1

公开(公告)日：2008-12-25

申请号：US11777388

申请日：2007-07-13

Applicant: Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

Inventor： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

IPC: H01L21/44 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract translation: 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20080001283A1

公开(公告)日：2008-01-03

申请号：US11679268

申请日：2007-02-27

Applicant: Ha Na LEE ,  Seung Taek YANG

Inventor： Ha Na LEE ,  Seung Taek YANG

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack package includes a base substrate having connection pads on an upper surface thereof and ball lands on a lower surface thereof; at least two semiconductor chips stacked by intervening a spacer on the base substrate and defined with through-holes for electrical connections on positions corresponding to the connection pads; electrical connection members for electrically connecting the stacked semiconductor chips and the base substrate to each other; a pair of heat sinks formed such that they contact the side surfaces of the stacked semiconductor chips and extend in a direction perpendicular to the base substrate; and outside connection terminals attached to the ball lands located on the lower surface of the base substrate.

Abstract translation: 堆叠封装包括在其上表面上具有连接焊盘的基底基板，并且在其下表面上具有焊盘; 至少两个半导体芯片通过在基底衬底上插入间隔物并且与对应于连接焊盘的位置上的用于电气连接的通孔间隔开来堆叠; 用于将堆叠的半导体芯片和基底基板彼此电连接的电连接构件; 一对散热片形成为使得它们接触堆叠的半导体芯片的侧表面并且在垂直于基底基板的方向上延伸; 以及附接到位于基底基板的下表面上的球接头的外部连接端子。

公开(公告)号：US20240140624A1

公开(公告)日：2024-05-02

申请号：US18406214

申请日：2024-01-08

Applicant: Ha Na LEE

Inventor： Ha Na LEE ,  Jong Jin LEE

IPC: B64U20/80 ,  G05D1/86

CPC classification number: B64U20/80 ,  G05D1/86 ,  B64U2201/00

Abstract: A drone integrated control device that controls a drone by unifying respective components on one board includes a flight control unit including a plurality of sensors and configured to control a path and a flight attitude of the drone, a motor control unit configured to control a rotation speed of at least one motor mounted to perform movements and takeoffs of the drone, a communication unit configured to transmit and receive control signals input to and output from the respective components included in the drone integrated control device, and a power supply unit configured to supply power to the respective components included in the drone integrated control device to operate the respective components.

公开(公告)号：US20090197372A1

公开(公告)日：2009-08-06

申请号：US12345858

申请日：2008-12-30

Applicant: Kwon Whan HAN ,  Chang Jun PARK ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE

Inventor： Kwon Whan HAN ,  Chang Jun PARK ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE

IPC: H01L21/00

CPC classification number: H01L24/16 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/17 ,  H01L24/90 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

Abstract: Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.

Abstract translation: 制造晶片级堆叠封装包括对包括多个第一半导体芯片的晶片的下表面进行背面磨削的步骤。 支撑构件附接到后磨碎晶片的下表面。 一个或多个第二半导体芯片堆叠在背面研磨的晶片的相应的第一半导体芯片上。 形成第一贯通电极以电连接堆叠的第一半导体芯片和第二半导体芯片。 第三半导体芯片附着到堆叠的第二半导体芯片的最上面，第三半导体芯片具有与连接到第二贯通电极的第一贯通电极和再分配线电连接的第二贯通电极。 外部连接端子附接到第三半导体芯片的再分配线路。 第二半导体芯片和第三半导体芯片堆叠的晶片级的第一半导体芯片在芯片级被锯切以用于半导体封装。

公开(公告)号：US20090184414A1

公开(公告)日：2009-07-23

申请号：US12347020

申请日：2008-12-31

Applicant: Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L23/04 ,  H01L23/12 ,  H01L21/00 ,  H01L23/482 ,  H01L21/98

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract translation: 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。