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15 条记录 (耗时 0.012 秒)

    Multilayer wiring board
    2.
    发明授权
    Multilayer wiring board 有权
    多层接线板

    公开(公告)号：US09119333B2

    公开(公告)日：2015-08-25

    申请号：US13399547

    申请日：2012-02-17

    申请人： Takuya Hando ,  Masahiro Inoue ,  Hajime Saiki ,  Atsuhiko Sugimoto ,  Hidetoshi Wada

    发明人： Takuya Hando ,  Masahiro Inoue ,  Hajime Saiki ,  Atsuhiko Sugimoto ,  Hidetoshi Wada

    IPC分类号： H05K3/40 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H05K3/46 ,  H05K3/00

    CPC分类号： H05K3/4007 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/01084 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/0367

    摘要： A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.

    摘要翻译： 一种多层布线基板，包括由一层或多层导体和树脂绝缘层形成的堆积层，所述导体和树脂绝缘层层叠在另一层之上，具有形成在至少一层树脂绝缘层的表面上的导电焊盘，以便从 提供表面。 导电垫可以各自包括位于其下部的柱状部分和位于其较高部分的凸部，其中凸部的表面可以呈现连续的弯曲形状。 可以在导电焊盘的上表面上形成焊料层。 某些实施例使得可以最小化或消除导电焊盘上的应力集中，并且可以抑制对半导体元件的不良连接的发生以及对导电焊盘的损坏。

    Taphole mix for molten metal taphole
    5.
    发明授权
    Taphole mix for molten metal taphole 失效
    用于熔融金属出铁口的混合孔

    公开(公告)号：US5962357A

    公开(公告)日：1999-10-05

    申请号：US83997

    申请日：1998-05-26

    申请人： Yukitoshi Kubota ,  Hidetoshi Wada ,  Yoshiyuki Nobuoka

    发明人： Yukitoshi Kubota ,  Hidetoshi Wada ,  Yoshiyuki Nobuoka

    IPC分类号： C04B35/66 ,  C04B35/52

    CPC分类号： C04B35/013 ,  C04B35/66 ,  C04B2235/3206 ,  C04B2235/3217 ,  C04B2235/3826 ,  C04B2235/3873 ,  C04B2235/422

    摘要： The object of the present invention is to provide a taphole mix for use in a molten metal taphole which has improved resistance to both wear and corrosion and enables prolonged tapping of iron and reduces difficult drilling. The taphole mix of the present invention is characterized in that it comprises a refractory base material in an amount of 65 to 92 wt % and a binder in an amount of 8 to 35 wt %, the binder consisting of an anhydrous coal tar having a fixed carbon content of 32.5 wt % or above.

    摘要翻译： 本发明的目的是提供一种用于熔融金属出料口的出钢混合物，其具有改善的耐磨性和耐腐蚀性，并且能够延长铁的剥离并且减少难以钻孔。 本发明的出钢混合物的特征在于，其含有65至92重量％的耐火材料和8至35重量％的粘合剂，该粘合剂由具有固定的无水煤焦油 碳含量为32.5重量％以上。

    Delay apparatus
    6.
    发明授权
    Delay apparatus 失效
    延迟装置

    公开(公告)号：US5313438A

    公开(公告)日：1994-05-17

    申请号：US78781

    申请日：1993-06-16

    申请人： Teruo Hieda ,  Hidetoshi Wada

    发明人： Teruo Hieda ,  Hidetoshi Wada

    IPC分类号： H04N9/64 ,  G11C27/04 ,  H03H11/26 ,  H03H15/02 ,  H04N5/14 ,  G11C13/00

    CPC分类号： G11C27/04 ,  H04N5/14

    摘要： A delay apparatus comprises one or a plurality of shift registers, a plurality of signal accumulating capacitors which are mutually coupled by transfer transistors, a plurality of write switches each of which is arranged between an input terminal and either one of the capacitors and which are controlled by outputs of the shift registers, and a plurality of read switches which are arranged between the plurality of capacitors and an output terminal and are controlled by the outputs of the shift registers, wherein the signal charges accumulated in the one capacitor are capacitively divided into other capacitors through the transfer transistors for transferring the signal charges.

    摘要翻译： 延迟装置包括一个或多个移位寄存器，由传输晶体管相互耦合的多个信号累积电容器，多个写开关，每个写开关布置在输入端子和电容器中的任一个之间并被控制 通过移位寄存器的输出，以及多个读取开关，其布置在多个电容器和输出端子之间，并且由移位寄存器的输出控制，其中累积在一个电容器中的信号电荷被电容性地划分为另一个 电容通过传输晶体管传送信号电荷。

    MULTILAYER WIRING BOARD
    7.
    发明申请
    MULTILAYER WIRING BOARD 有权
    多层接线板

    公开(公告)号：US20120186863A1

    公开(公告)日：2012-07-26

    申请号：US13355916

    申请日：2012-01-23

    申请人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Takuya HANDO ,  Hidetoshi WADA

    发明人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Takuya HANDO ,  Hidetoshi WADA

    IPC分类号： H05K1/02

    CPC分类号： H05K1/111 ,  H01L23/12 ,  H01L23/32 ,  H01L24/00 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H05K1/113 ,  H05K3/0097 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/09745 ,  Y02P70/611

    摘要： A multilayer wiring board including a build-up layer comprising a conductor layer and a resin insulation layer that are alternately layered, conductive pads formed on a surface of a resin insulation layer so as to project from the surface, and a solder layer formed over an upper surface of each of the conductive pads is provided. The upper surface of the conductive pads may have a recess, and the entire surface of the solder layer may be situated at an elevated position with respect to an outer periphery portion of the upper surface. Embodiments make it possible to feed and hold a sufficient amount of solder paste on the upper surface of conductive pads, thereby minimizing or eliminating the occurrence of defective connections to a semiconductor element and damage to the solder layer caused by an insufficient thickness of the solder layer.

    摘要翻译： 一种多层布线基板，包括：交替层叠导体层和树脂绝缘层的堆积层，形成在表面突出的树脂绝缘层的表面的导电性焊盘，以及形成在 提供每个导电焊盘的上表面。 导电焊盘的上表面可以具有凹部，并且焊料层的整个表面可以相对于上表面的外周部分位于升高位置。 实施例使得可以在导电焊盘的上表面上馈送和保持足够量的焊膏，从而最小化或消除与半导体元件的不良连接的发生以及由焊料层的厚度不足引起的焊料层的损坏 。

    Image sensing apparatus and method having noise reduction function
    8.
    发明授权
    Image sensing apparatus and method having noise reduction function 失效
    具有降噪功能的图像感测装置和方法

    公开(公告)号：US06803953B2

    公开(公告)日：2004-10-12

    申请号：US09794472

    申请日：2001-02-27

    申请人： Hidetoshi Wada

    发明人： Hidetoshi Wada

    IPC分类号： H04N5217

    CPC分类号： H04N5/23258 ,  H04N5/217 ,  H04N5/23248 ,  H04N5/23267 ,  H04N9/045

    摘要： In an image sensing apparatus which performs noise reduction processing using pixel signals obtained by consecutively scanning a CCD image sensor at different timings, for performing image expansion in the vertical direction by controlling scanning of the CCD image sensor, an area to be read in the CCD image sensor is set on the basis of an expansion ratio. Pixel signal which have undergone the noise reduction processing and stored in advance in a memory are read so that colors of corresponding pixel signals do not shift. The noise reduction processing is performed on the current pixel signals read from the set area using the pixel signals read from the memory. The noise-reduced pixel signals are stored in the memory, and used in the next noise reduction processing for pixel signals read from the CCD image sensor of the next period.

    摘要翻译： 在利用通过在不同时刻连续地扫描CCD图像传感器而获得的像素信号进行降噪处理的图像感测装置中，通过控制CCD图像传感器的扫描来进行垂直方向的图像扩展，在CCD中读取的区域 图像传感器基于膨胀比设定。 已经经历了降噪处理并预先存储在存储器中的像素信号被读取，使得对应的像素信号的颜色不发生偏移。 使用从存储器读取的像素信号对从设定区域读取的当前像素信号执行噪声降低处理。 噪声降低的像素信号被存储在存储器中，并且用于下一个从下一个周期的CCD图像传感器读取的像素信号的降噪处理。

    MULTILAYER WIRING BOARD
    10.
    发明申请
    MULTILAYER WIRING BOARD 有权
    多层接线板

    公开(公告)号：US20120211271A1

    公开(公告)日：2012-08-23

    申请号：US13399547

    申请日：2012-02-17

    申请人： Takuya HANDO ,  Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Hidetoshi WADA

    发明人： Takuya HANDO ,  Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Hidetoshi WADA

    IPC分类号： H05K1/02

    CPC分类号： H05K3/4007 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/01084 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/0367

    摘要： A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.

    摘要翻译： 一种多层布线基板，包括由一层或多层导体和树脂绝缘层形成的堆积层，所述导体和树脂绝缘层层叠在另一层之上，具有形成在至少一层树脂绝缘层的表面上的导电焊盘，以便从 提供表面。 导电垫可以各自包括位于其下部的柱状部分和位于其较高部分的凸部，其中凸部的表面可以呈现连续的弯曲形状。 可以在导电焊盘的上表面上形成焊料层。 某些实施例使得可以最小化或消除导电焊盘上的应力集中，并且可以抑制对半导体元件的不良连接的发生以及对导电焊盘的损坏。