公开(公告)号：US20110155438A1

公开(公告)日：2011-06-30

申请号：US12978750

申请日：2010-12-27

申请人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

发明人： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

IPC分类号： H05K1/11

CPC分类号： H05K3/4682 ,  H05K1/113 ,  H05K3/4007 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/09472

摘要： A multilayer wiring substrate has a multilayer wiring laminate portion in which a plurality of resin insulation layers made primarily of the same resin insulation material, and a plurality of conductive layers are laminated alternately. A plurality of first-main-surface-side connection terminals are disposed on one side of the laminate structure where a first main surface thereof is present, and a plurality of second-main-surface-side connection terminals being disposed on an other side of the laminate structure where a second main surface thereof is present. The plurality of conductive layers are formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface or the second main surface. The plurality of first-main-surface-side connection terminals comprising at least two types of terminals for connection of different articles-to-be-connected. Top surfaces of the plurality of first-main-surface-side connection terminals differ in height according to types of the articles-to-be-connected.

摘要翻译： 多层布线基板具有多层布线层叠部，其中主要由相同树脂绝缘材料制成的多个树脂绝缘层和多个导电层交替层叠。 多个第一主表面侧连接端子设置在层叠结构的存在第一主表面的一侧上，并且多个第二主表面侧连接端子设置在 其中存在第二主表面的层压结构。 多个导电层形成在多个树脂绝缘层中，并且通过直径朝向第一主表面或第二主表面增大的通孔导体互连。 多个第一主表面侧连接端子包括用于连接不同待连接物品的至少两种类型的端子。 多个第一主表面侧连接端子的顶表面根据要连接的物品的类型而不同。

公开(公告)号：US07122894B2

公开(公告)日：2006-10-17

申请号：US11071203

申请日：2005-03-04

申请人： Atsuhiko Sugimoto ,  Hajime Saiki

发明人： Atsuhiko Sugimoto ,  Hajime Saiki

IPC分类号： H01L23/48

CPC分类号： H05K3/244 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/3457 ,  H01L2924/00

摘要： A wiring substrate incorporating nickel-plated copper terminal pads for solder bumps, wherein a nickel plating layer constituting the nickel plated copper terminal pads has a phosphorus content of 8.5 to 15.0% by mass and is covered with a gold plating layer.

摘要翻译： 包括用于焊料凸块的镀镍铜端子焊盘的布线基板，其中构成镀镍铜端子焊盘的镀镍层的磷含量为8.5〜15.0质量％，被镀金层覆盖。

公开(公告)号：US08937256B2

公开(公告)日：2015-01-20

申请号：US13353965

申请日：2012-01-19

申请人： Masahiro Inoue ,  Hajime Saiki ,  Atsuhiko Sugimoto

发明人： Masahiro Inoue ,  Hajime Saiki ,  Atsuhiko Sugimoto

IPC分类号： H01K1/02 ,  H05K13/04 ,  H05K3/34 ,  H01L23/00

CPC分类号： H05K3/3478 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/16225 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H01L2924/00

摘要： A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.

摘要翻译： 本发明提供一种电子部件安装用布线基板的制造方法，电子部件的安装用布线基板以及电子元件搭载布线基板的制造方法。 可以将包括焊料和由树脂制成的电绝缘材料的接合材料糊料放置在芯片安装端子焊盘上并加热以熔化焊料并软化电绝缘材料。 随后，焊料固化形成焊料凸块。 此外，电绝缘材料在每个焊料凸块的表面和每个焊料凸块周围的多层板的表面上固化，以形成电绝缘表面层。 因此，当芯片安装到这种布线板时，电绝缘表面层在焊料的再熔合期间使相邻焊料凸块之间的连接最小化或消除。

公开(公告)号：US20120211271A1

公开(公告)日：2012-08-23

申请号：US13399547

申请日：2012-02-17

申请人： Takuya HANDO ,  Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Hidetoshi WADA

发明人： Takuya HANDO ,  Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Hidetoshi WADA

IPC分类号： H05K1/02

CPC分类号： H05K3/4007 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/01084 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/0367

摘要： A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.

摘要翻译： 一种多层布线基板，包括由一层或多层导体和树脂绝缘层形成的堆积层，所述导体和树脂绝缘层层叠在另一层之上，具有形成在至少一层树脂绝缘层的表面上的导电焊盘，以便从 提供表面。 导电垫可以各自包括位于其下部的柱状部分和位于其较高部分的凸部，其中凸部的表面可以呈现连续的弯曲形状。 可以在导电焊盘的上表面上形成焊料层。 某些实施例使得可以最小化或消除导电焊盘上的应力集中，并且可以抑制对半导体元件的不良连接的发生以及对导电焊盘的损坏。

公开(公告)号：US20120186864A1

公开(公告)日：2012-07-26

申请号：US13354043

申请日：2012-01-19

申请人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO

发明人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO

IPC分类号： H05K1/02 ,  H05K3/46

CPC分类号： B23K1/00 ,  B23K35/22 ,  B23K35/26 ,  C22C11/06 ,  C22C13/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68318 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68386 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2924/15174 ,  H01L2924/15312 ,  H05K3/4682 ,  H05K2201/10318 ,  H01L2924/014

摘要： A wiring board and a method for manufacturing the wiring board reinforced by means of a resin is provided. Embodiments of the wiring board allow for reliable attachment of a connection member, like a socket, to a terminal member. For example, a base of terminal pins is put on pin grid array (PGA) terminal pads, and a bonding material paste including solder and an electric insulation material made of a resin is placed on each of the PGA terminal pads. The bonding material paste is then heated to fuse the solder and soften the electric insulation material. Subsequently, the bonding material paste is cooled to solidify the solder and bond each of the bases to a corresponding PGA terminal pad and form an electric insulation surface layer on an exposed surface of each of solder junctions to which the respective bases are bonded.

摘要翻译： 提供了一种通过树脂加强的布线板和制造布线板的方法。 布线板的实施例允许将连接构件（如插座）可靠地附接到端子构件。 例如，将端子引脚的基座放置在引脚格栅阵列（PGA）端子焊盘上，并且将包含焊料的接合材料浆料和由树脂制成的电绝缘材料放置在每个PGA端子焊盘上。 然后将接合材料浆料加热以熔化焊料并软化电绝缘材料。 随后，将接合材料浆料冷却以固化焊料，并将每个基底结合到相应的PGA端子焊盘上，并在各个基底所接合的每个焊接点的暴露表面上形成电绝缘表面层。

公开(公告)号：US20120186857A1

公开(公告)日：2012-07-26

申请号：US13353965

申请日：2012-01-19

申请人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO

发明人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO

IPC分类号： H05K1/02 ,  H05K13/04

CPC分类号： H05K3/3478 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/16225 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H01L2924/00

摘要： A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.

摘要翻译： 本发明提供一种电子部件安装用布线基板的制造方法，电子部件的安装用布线基板以及电子元件搭载布线基板的制造方法。 可以将包括焊料和由树脂制成的电绝缘材料的接合材料糊料放置在芯片安装端子焊盘上并加热以熔化焊料并软化电绝缘材料。 随后，焊料固化形成焊料凸块。 此外，电绝缘材料在每个焊料凸块的表面和每个焊料凸块周围的多层板的表面上固化，以形成电绝缘表面层。 因此，当芯片安装到这种布线板时，电绝缘表面层在焊料的再熔合期间使相邻焊料凸块之间的连接最小化或消除。

公开(公告)号：US20110156272A1

公开(公告)日：2011-06-30

申请号：US12976427

申请日：2010-12-22

申请人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

发明人： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

IPC分类号： H01L23/48

CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

摘要： A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

摘要翻译： 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

公开(公告)号：US07202156B2

公开(公告)日：2007-04-10

申请号：US10989515

申请日：2004-11-17

申请人： Hajime Saiki ,  Atsuhiko Sugimoto ,  Mikiya Sakurai

发明人： Hajime Saiki ,  Atsuhiko Sugimoto ,  Mikiya Sakurai

IPC分类号： H01L21/4763

CPC分类号： H05K3/4661 ,  H05K3/108 ,  H05K3/181 ,  H05K3/4602 ,  H05K2201/0209

摘要： A process for manufacturing a wiring substrate, comprising: a step of forming an insulating resin layer containing an inorganic filler over a wiring layer formed on at least one surface of an insulating substrate; a step of forming a thin copper film layer by roughening a surface of the insulating resin layer and plating the same electrolessly with copper; a step of forming an insulating film over the thin copper film layer; a step of forming plated resists profiling a pattern by exposing and developing the insulating film with the pattern; and a step of forming wiring pattern layers by an electrolytic copper plating on a surface of the insulating resin layer having the plated resists formed thereon, wherein at least one of the plated resists has a width of less than 20 μm, and the plated resists include adjoining plated resists in which a clearance between said adjoining plated resists has a width of less than 20 μm.

摘要翻译： 一种布线基板的制造方法，包括：在绝缘基板的至少一个面上形成的布线层上形成含有无机填料的绝缘树脂层的工序; 通过使绝缘树脂层的表面粗糙化并用铜电化而使其形成薄铜膜层的步骤; 在所述薄铜膜层上形成绝缘膜的步骤; 通过用图案曝光和显影绝缘膜来形成电镀抗蚀剂的步骤; 以及在其上形成有电镀抗蚀剂的绝缘树脂层的表面上通过电解铜电镀形成布线图案层的步骤，其中至少一个电镀抗蚀剂具有小于20μm的宽度，并且电镀抗蚀剂包括 邻接的电镀抗蚀剂，其中所述相邻的电镀抗蚀剂之间的间隙具有小于20μm的宽度。

公开(公告)号：US08319111B2

公开(公告)日：2012-11-27

申请号：US11865919

申请日：2007-10-02

申请人： Hajime Saiki ,  Mikiya Sakurai ,  Atsuhiko Sugimoto

发明人： Hajime Saiki ,  Mikiya Sakurai ,  Atsuhiko Sugimoto

IPC分类号： H05K1/03

CPC分类号： H05K1/115 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2203/0733 ,  H01L2924/00

摘要： A wiring board having a favorable electrical reliability and in which a crack is unlikely to occur at a connection interface of via conductors even though the number of via conductors in series, which constitutes the stacked via, becomes larger than that of a conventional wiring board.

摘要翻译： 即使构成堆叠通孔的串联的通孔导体的数量变得比常规的布线板大，因此具有良好的电气可靠性并且在通孔导体的连接界面处不可能发生裂纹的布线板。

公开(公告)号：US20120186863A1

公开(公告)日：2012-07-26

申请号：US13355916

申请日：2012-01-23

申请人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Takuya HANDO ,  Hidetoshi WADA

发明人： Masahiro INOUE ,  Hajime SAIKI ,  Atsuhiko SUGIMOTO ,  Takuya HANDO ,  Hidetoshi WADA

IPC分类号： H05K1/02

CPC分类号： H05K1/111 ,  H01L23/12 ,  H01L23/32 ,  H01L24/00 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H05K1/113 ,  H05K3/0097 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/09745 ,  Y02P70/611

摘要： A multilayer wiring board including a build-up layer comprising a conductor layer and a resin insulation layer that are alternately layered, conductive pads formed on a surface of a resin insulation layer so as to project from the surface, and a solder layer formed over an upper surface of each of the conductive pads is provided. The upper surface of the conductive pads may have a recess, and the entire surface of the solder layer may be situated at an elevated position with respect to an outer periphery portion of the upper surface. Embodiments make it possible to feed and hold a sufficient amount of solder paste on the upper surface of conductive pads, thereby minimizing or eliminating the occurrence of defective connections to a semiconductor element and damage to the solder layer caused by an insufficient thickness of the solder layer.

摘要翻译： 一种多层布线基板，包括：交替层叠导体层和树脂绝缘层的堆积层，形成在表面突出的树脂绝缘层的表面的导电性焊盘，以及形成在 提供每个导电焊盘的上表面。 导电焊盘的上表面可以具有凹部，并且焊料层的整个表面可以相对于上表面的外周部分位于升高位置。 实施例使得可以在导电焊盘的上表面上馈送和保持足够量的焊膏，从而最小化或消除与半导体元件的不良连接的发生以及由焊料层的厚度不足引起的焊料层的损坏 。