公开(公告)号：US20080145589A1

公开(公告)日：2008-06-19

申请号：US11870620

申请日：2007-10-11

Applicant: Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

Inventor： Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

IPC: B32B1/02

CPC classification number: H05K1/144 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K2201/042 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T428/23 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An electronic package is provided. The electronic package includes a first substrate, an electronic component, a first sealant, a second substrate, a plurality of bonding wires and a second sealant, wherein the first substrate has opposing upper and lower surfaces and a plurality of bonding pads is disposed on the upper surface of the first substrate. The electronic component is positioned on the upper surface of the first substrate and electrically connected to the bonding pads. The first sealant is formed on the upper surface of the first substrate to encapsulate the electronic component. The lower surface of the second substrate is attached to the first sealant. The upper surface of the second substrate includes a central protrusion and a rim portion which surrounds and is lower than the central protrusion. A plurality of bonding wires is used to electrically connect the rim portion to the first substrate. The second sealant is formed on the upper surface of the first substrate and on the rim portion of the second substrate to encapsulate the bonding wires, the first sealant and the rim portion.

Abstract translation: 提供电子包装。 电子封装包括第一基板，电子部件，第一密封剂，第二基板，多个接合线和第二密封剂，其中第一基板具有相对的上表面和下表面，并且多个接合焊盘设置在 第一基板的上表面。 电子部件位于第一基板的上表面上并电连接到接合焊盘。 第一密封剂形成在第一基板的上表面上以封装电子部件。 第二基板的下表面附接到第一密封剂。 第二基板的上表面包括中心突起和围绕中心突起的边缘部分。 使用多个接合线将边缘部分电连接到第一基板。 第二密封剂形成在第一基板的上表面和第二基板的边缘部分上，以封装接合线，第一密封剂和边缘部分。

公开(公告)号：US07060595B2

公开(公告)日：2006-06-13

申请号：US10627609

申请日：2003-07-28

Applicant: In-De Ou ,  Chih-Pin Hung ,  Chia-Shang Chen ,  Kuang-Hua Lin ,  Shin-Hua Chao

Inventor： In-De Ou ,  Chih-Pin Hung ,  Chia-Shang Chen ,  Kuang-Hua Lin ,  Shin-Hua Chao

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/043 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H01L2924/00

Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.

Abstract translation: 电路基板包括板，多个金属层和绝缘体。 该板具有多个导电迹线层和形成在其中的通孔。 金属层形成在通孔的内壁上，并且每个金属层电连接到其对应的导电迹线层。 通孔填充有绝缘体，使得每个金属层彼此电隔离。 此外，本发明还提供了电路基板的制造方法。

公开(公告)号：US20080273313A1

公开(公告)日：2008-11-06

申请号：US12078330

申请日：2008-03-28

Applicant: Yung-Hui Wang ,  In-De Ou ,  Chih-Pin Hung

Inventor： Yung-Hui Wang ,  In-De Ou ,  Chih-Pin Hung

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/14 ,  H05K3/4602 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/1178 ,  Y02P70/611 ,  H01L2924/00

Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.

Abstract translation: 具有嵌入式部件的载体包括基板和至少一个嵌入部件。 衬底具有至少一个槽和第一复合层。 嵌入式部件设置在基板的狭槽处。 第一复合层具有脱气结构，至少一个第一通孔和至少一个第一紧固件，其中脱气结构对应于槽，第一通孔暴露嵌入的部件，并且第一紧固件形成在第一通孔 孔并与嵌入式组件接触。 根据本发明，脱气结构能够在高温环境下平稳地排出存在于载体内的水圈，并且第一紧固件与嵌入部件接触，这增加了嵌入部件和基板之间的接合强度。

公开(公告)号：US07256480B2

公开(公告)日：2007-08-14

申请号：US11164823

申请日：2005-12-07

Applicant: Chih-Pin Hung ,  In-De Ou

Inventor： Chih-Pin Hung ,  In-De Ou

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame package structure with high density of lead pins arrangement is formed. The lead frame structure includes a die, a plurality of first lead pins and a plurality of second lead pins, wherein the first lead pins and the second lead pins are positioned on at least one side of the die, and are electrically connected to the die. The first lead pins and the second lead pins are selected from a group consisting of J-leads, L-leads and I-leads, and terminals of the first lead pins and terminals of the second lead pins are staggered so that the high density of lead pins arrangement is formed without risking a short circuit.

Abstract translation: 形成具有高密度引线引脚布置的引线框封装结构。 引线框架结构包括管芯，多个第一引线引脚和多个第二引线引脚，其中第一引线引脚和第二引线引脚位于管芯的至少一侧，并且电连接到管芯 。 第一引线引脚和第二引线引脚选自由J引脚，L引脚和I引线组成的组，并且第一引线引脚的端子和第二引脚引脚的端子交错，使得高密度 引脚引脚布置形成，不会有短路的危险。

公开(公告)号：US20070080431A1

公开(公告)日：2007-04-12

申请号：US11164823

申请日：2005-12-07

Applicant: Chih-Pin Hung ,  In-De Ou

Inventor： Chih-Pin Hung ,  In-De Ou

IPC: H01L23/495 ,  H01L23/52

CPC classification number: H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame package structure with high density of lead pins arrangement is formed. The lead frame structure includes a die, a plurality of first lead pins and a plurality of second lead pins, wherein the first lead pins and the second lead pins are positioned on at least one side of the die, and are electrically connected to the die. The first lead pins and the second lead pins are selected from a group consisting of J-leads, L-leads and I-leads, and terminals of the first lead pins and terminals of the second lead pins are staggered so that the high density of lead pins arrangement is formed without risking a short circuit.

Abstract translation: 形成具有高密度引线引脚布置的引线框封装结构。 引线框架结构包括管芯，多个第一引线引脚和多个第二引线引脚，其中第一引线引脚和第二引线引脚位于管芯的至少一侧，并且电连接到管芯 。 第一引线引脚和第二引线引脚选自由J引脚，L引脚和I引线组成的组，并且第一引线引脚和第二引脚引脚的端子的端子交错，使得高密度 引脚引脚布置形成，不会有短路的危险。

公开(公告)号：US06680529B2

公开(公告)日：2004-01-20

申请号：US10075227

申请日：2002-02-15

Applicant: Kun-Ching Chen ,  Yi-Chuan Ding ,  In-De Ou

Inventor： Kun-Ching Chen ,  Yi-Chuan Ding ,  In-De Ou

IPC: H01L2334

CPC classification number: H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract translation: 半导体积层封装包括管芯，电路板和至少介电层。 电路板具有用于构建电介质层的表面，并且该表面具有用于容纳模具的空腔。 多层电路板的内部具有扩展半导体集成封装的电气功能的导电迹线。 每个电介质层具有导电柱，使得管芯可以与最外层电介质层电连接。 至少导电柱结合在多层电路板的表面上用于内部电连接。

公开(公告)号：US08000107B2

公开(公告)日：2011-08-16

申请号：US12078330

申请日：2008-03-28

Applicant: Yung-Hui Wang ,  In-De Ou ,  Chih-Pin Hung

Inventor： Yung-Hui Wang ,  In-De Ou ,  Chih-Pin Hung

IPC: H01L23/495

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/14 ,  H05K3/4602 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/1178 ,  Y02P70/611 ,  H01L2924/00

Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.

Abstract translation: 具有嵌入式部件的载体包括基板和至少一个嵌入部件。 衬底具有至少一个槽和第一复合层。 嵌入式部件设置在基板的狭槽处。 第一复合层具有脱气结构，至少一个第一通孔和至少一个第一紧固件，其中脱气结构对应于槽，第一通孔暴露嵌入的部件，并且第一紧固件形成在第一通孔 孔并与嵌入式组件接触。 根据本发明，脱气结构能够在高温环境下平稳地排出存在于载体内的水圈，并且第一紧固件与嵌入部件接触，这增加了嵌入部件和基板之间的接合强度。

公开(公告)号：US07586184B2

公开(公告)日：2009-09-08

申请号：US11870620

申请日：2007-10-11

Applicant: Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

Inventor： Chih Pin Hung ,  Chi Tsung Chiu ,  In De Ou ,  Yung Hui Wang

IPC: H01L23/498

CPC classification number: H05K1/144 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K2201/042 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T428/23 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An electronic package is provided. The electronic package includes a first substrate, an electronic component, a first sealant, a second substrate, a plurality of bonding wires and a second sealant, wherein the first substrate has opposing upper and lower surfaces and a plurality of bonding pads is disposed on the upper surface of the first substrate. The electronic component is positioned on the upper surface of the first substrate and electrically connected to the bonding pads. The first sealant is formed on the upper surface of the first substrate to encapsulate the electronic component. The lower surface of the second substrate is attached to the first sealant. The upper surface of the second substrate includes a central protrusion and a rim portion which surrounds and is lower than the central protrusion. A plurality of bonding wires is used to electrically connect the rim portion to the first substrate. The second sealant is formed on the upper surface of the first substrate and on the rim portion of the second substrate to encapsulate the bonding wires, the first sealant and the rim portion.

Abstract translation: 提供电子包装。 电子封装包括第一基板，电子部件，第一密封剂，第二基板，多个接合线和第二密封剂，其中第一基板具有相对的上表面和下表面，并且多个接合焊盘设置在 第一基板的上表面。 电子部件位于第一基板的上表面上并电连接到接合焊盘。 第一密封剂形成在第一基板的上表面上以封装电子部件。 第二基板的下表面附接到第一密封剂。 第二基板的上表面包括中心突起和围绕中心突起的边缘部分。 使用多个接合线将边缘部分电连接到第一基板。 第二密封剂形成在第一基板的上表面和第二基板的边缘部分上，以封装接合线，第一密封剂和边缘部分。

公开(公告)号：US06701614B2

公开(公告)日：2004-03-09

申请号：US10075231

申请日：2002-02-15

Applicant: Yi-Chuan Ding ,  In-De Ou ,  Kun-Ching Chen

Inventor： Yi-Chuan Ding ,  In-De Ou ,  Kun-Ching Chen

IPC: H01K322

CPC classification number: H01L24/97 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/0733 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract translation: 一种用于制造半导体管芯的堆积封装的方法和由其形成的结构。 具有导电柱的铜箔通过热压合而结合到封装的管芯上，其间夹有预固化电介质膜。 电介质膜被固化以形成模具积聚封装的电介质层，并且蚀刻介电层上的铜箔以形成导电迹线。 电介质层之一中的至少一个导电柱垂直对应于相邻电介质层中的导电柱之一。

公开(公告)号：US06750397B2

公开(公告)日：2004-06-15

申请号：US10075226

申请日：2002-02-15

Applicant: In-De Ou ,  Yi-Chuan Ding ,  Kun-Ching Chen

Inventor： In-De Ou ,  Yi-Chuan Ding ,  Kun-Ching Chen

IPC: H01L2302

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L24/19 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract translation: 半导体积层封装包括管芯，金属载体和多个电介质层。 金属载体具有用于支撑模具的空腔的表面。 金属载体的表面与用于建立多个电介质层的管芯的有源表面共面。 每个电介质层具有用于内部电连接的金属柱。 金属载体覆盖模具的被动表面和侧面，具有较大的散热面积，因此从模具产生的热量通过金属载体快速消散。