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177 条记录 (耗时 0.028 秒)

    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
    6.
    发明授权
    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices 有权
    阻挡金属层反向电镀以提高铜互连器件的电迁移性能

    公开(公告)号：US06261963B1

    公开(公告)日：2001-07-17

    申请号：US09611729

    申请日：2000-07-07

    申请人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    发明人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    IPC分类号： H01L21302

    CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  Y10S438/927

    摘要： A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

    摘要翻译： 提供了一种用于形成导电互连的方法，所述方法包括在结构层上形成第一介电层，在第一介电层中形成第一开口，并在第一开口中形成第一导电结构。 该方法还包括在第一介电层之上和第一导电结构之上形成第二电介质层，在第二导电结构的至少一部分上方的第二电介质层中形成第二开口，第二开口具有侧表面和 并且在侧表面和底表面上的第二开口中形成至少一个阻挡金属层。 此外，该方法包括从底表面去除至少一个阻挡金属层的一部分，以及在第二开口中形成第二导电结构，第二导电结构与第一导电结构的至少一部分接触。 该方法还包括通过使第二导电结构和第一导电结构退火来形成导电互连。

    Semiconductor device with partial passivation layer
    7.
    发明授权
    Semiconductor device with partial passivation layer 有权
    具有部分钝化层的半导体器件

    公开(公告)号：US06313538B1

    公开(公告)日：2001-11-06

    申请号：US09489479

    申请日：2000-01-21

    申请人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    发明人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

    摘要翻译： 半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层 。 一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质 并且与钝化层和第一介电层接触。

    Photoresist removal using a polishing tool
    8.
    发明授权
    Photoresist removal using a polishing tool 有权
    使用抛光工具去除光刻胶

    公开(公告)号：US06315637B1

    公开(公告)日：2001-11-13

    申请号：US09484601

    申请日：2000-01-18

    申请人： Eric M. Apelgren ,  Jonathan B. Smith ,  Paul R. Besser

    发明人： Eric M. Apelgren ,  Jonathan B. Smith ,  Paul R. Besser

    IPC分类号： B24B100

    CPC分类号： H01L21/31058 ,  B24B37/042

    摘要： The present invention is directed to semiconductor processing operations. In one illustrative embodiment, the invention comprises providing a wafer having a layer of photoresist formed thereabove, positioning the layer of photoresist in contact with a polishing pad or a polishing tool, and rotating at least one of the wafer and the polishing pad to remove substantially all of the layers of photoresist.

    摘要翻译： 本发明涉及半导体处理操作。 在一个说明性实施例中，本发明包括提供具有在其上形成的光致抗蚀剂层的晶片，将光致抗蚀剂层定位成与抛光垫或抛光工具接触，并且旋转晶片和抛光垫中的至少一个，以基本上去除 所有的光刻胶层。

    Method of forming a semiconductor device with metal silicide regions
    9.
    发明授权
    Method of forming a semiconductor device with metal silicide regions 有权
    用金属硅化物区形成半导体器件的方法

    公开(公告)号：US06268255B1

    公开(公告)日：2001-07-31

    申请号：US09479402

    申请日：2000-01-06

    申请人： Paul R. Besser ,  Christian Zistl ,  Nicholas J. Kepler

    发明人： Paul R. Besser ,  Christian Zistl ,  Nicholas J. Kepler

    IPC分类号： H01L21336

    CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/6659

    摘要： The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.

    摘要翻译： 本发明涉及制造半导体器件的方法。 在一个说明性实施例中，该方法包括形成由多晶硅组成的第一层，在多晶硅层上形成由难熔金属组成的第二层，并将第二层的至少一部分转化为第一金属硅化物。 该方法还包括在难熔金属层或第一金属硅化物层之上形成抗反射涂层，以及对第一金属硅化物层和多晶硅层进行构图以限定由第一金属硅化物区和 多晶硅层，在衬底中形成多个源极/漏极区域，在至少栅极堆叠和源极/漏极区域上形成由难熔金属组成的第三层，并将第三层的至少一部分转化为 第二金属硅化物区域。

    Dual slurry particle sizes for reducing microscratching of wafers
    10.
    发明授权
    Dual slurry particle sizes for reducing microscratching of wafers 有权
    用于减少晶片显微镜的双重浆料粒径

    公开(公告)号：US06294472B1

    公开(公告)日：2001-09-25

    申请号：US09576750

    申请日：2000-05-23

    申请人： Jonathan B. Smith ,  Paul R. Besser ,  Jeremy I. Martin

    发明人： Jonathan B. Smith ,  Paul R. Besser ,  Jeremy I. Martin

    IPC分类号： H01L2100

    CPC分类号： C09G1/02 ,  B24B37/044 ,  B24B57/02 ,  H01L21/30625

    摘要： A method includes providing at least one wafer having a process layer formed thereon for polishing. The process layer is polished using a first polishing process that is associated with a slurry having a first abrasive particle size. The process layer is polished using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon for polishing. The polishing tool is adapted to polish the process layer using a first polishing process that is associated with a slurry having a first abrasive particle size. The polishing tool is adapted to polish the process layer using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. The process controller is coupled to the polishing tool and adapted to communicate with at least one of a slurry controller and the polishing tool.

    摘要翻译： 一种方法包括提供至少一个晶片，其上形成有用于抛光的工艺层。 使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。 使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光方法来抛光工艺层。 系统包括抛光工具和过程控制器。 抛光工具适于接收至少一个晶片，其上形成有用于抛光的工艺层。 抛光工具适于使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。 抛光工具适于使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光工艺来抛光工艺层。 过程控制器耦合到抛光工具并且适于与浆料控制器和抛光工具中的至少一个连通。