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公开(公告)号:US20100155114A1
公开(公告)日:2010-06-24
申请号:US12659080
申请日:2010-02-24
IPC分类号: H05K1/03
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止或减轻用于安装半导体元件的半导体元件和半导体封装之间的接合部分中的应力的发生,使得即使安装具有低强度的半导体元件也不会发生裂纹。 半导体器件的封装形成为包括多个导电层和绝缘树脂层的多层的叠层,所述多个导电层和绝缘树脂层彼此交替层叠,并且在层叠体的一个表面上具有用于安装半导体元件的部分。 至少包括用于安装半导体元件的部分和其周边的层压体的绝缘树脂层的整个区域或某些区域由通过浸渍液晶聚合物的织物而获得的预浸料 绝缘树脂。
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公开(公告)号:US20060209497A1
公开(公告)日:2006-09-21
申请号:US10549079
申请日:2004-09-21
申请人: Kazuhiko Ooi , Kenjiro Enoki , Sachiko Oda
发明人: Kazuhiko Ooi , Kenjiro Enoki , Sachiko Oda
IPC分类号: H02B1/00
CPC分类号: H05K3/244 , C23C18/1651 , H01L23/49816 , H01L2924/0002 , H05K3/3457 , H05K2203/072 , H01L2924/00
摘要: A pad structure for a circuit board including a phosphorus-containing nickel layer is provided, capable of improving a tensile strength of a solder member such as a solder ball mounted thereon or a foreign member soldered thereto. The pad structure (40) is a multi-layer plated structure provided in a conductor pattern of the substrate, for mounting the solder bump (20) thereon, and formed as part of the conductor pattern, including a metal layer (10) formed as part of the conductor pattern to constitute a pad body, a phosphorus-containing nickel layer (12) formed by an electroless nickel plating to be directly brought into contact with the metal layer, a copper layer (14) thinner than the nickel layer, formed on the nickel layer by an electroless copper plating, and a precious metal layer (16) formed on the copper layer by an electroless precious metal plating.
摘要翻译: 提供了一种用于包括含磷镍层的电路板的焊盘结构,其能够提高焊接部件(例如安装在其上的焊球)或焊接的外部部件的抗拉强度。 衬垫结构(40)是设置在衬底的导体图案中的多层电镀结构,用于将焊料凸块(20)安装在其上,并形成为导体图案的一部分,包括金属层(10),其形成为 构成衬垫体的导体图案的一部分,通过化学镀镍形成的含磷镍层(12)与金属层直接接触,形成比镍层薄的铜层(14) 通过化学镀铜在镍层上,通过无电镀贵金属镀在铜层上形成的贵金属层(16)。
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公开(公告)号:US06767616B2
公开(公告)日:2004-07-27
申请号:US10436143
申请日:2003-05-13
申请人: Kazuhiko Ooi , Masaru Yamazaki , Yukiji Watanabe , Takaaki Yazawa
发明人: Kazuhiko Ooi , Masaru Yamazaki , Yukiji Watanabe , Takaaki Yazawa
IPC分类号: B32B300
CPC分类号: H05K3/44 , H05K3/429 , H05K3/4608 , H05K3/4641 , H05K2201/09518 , H05K2201/09554 , H05K2201/09563 , H05K2201/09718 , H05K2201/09809 , H05K2201/09827 , H05K2201/09845 , Y10S428/901 , Y10T428/24917
摘要: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43). The second metal plate (12) is electrically connected with the second wiring pattern (46) and the first wiring pattern (45), respectively, by means of a via (42) and by means a via (41), respectively.
摘要翻译: 金属芯基板包括由第一和第二金属板(11,12)组成的芯层(10),第一和第二金属板与第三绝缘层(13)分开; 分别形成在第一和金属板上的第一和第二绝缘层(20,21); 分别形成在第一和第二绝缘层上的第一和第二布线图案(45,46)。 形成在通孔(22)中的导电层(40)穿过第一绝缘层,第一金属板,第三绝缘层,第二金属板和第二绝缘层,用于将第一布线图案与第二绝缘层 接线图案。 第一金属板(11)通过通孔(44)和通孔(43)分别与第一布线图案(45)和第二布线图案(46)电连接。 第二金属板(12)分别通过通孔(42)和通孔(41)与第二布线图案(46)和第一布线图案(45)电连接。
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公开(公告)号:US20080042258A1
公开(公告)日:2008-02-21
申请号:US11892927
申请日:2007-08-28
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止或减轻用于安装半导体元件的半导体元件和半导体封装之间的接合部分中的应力的发生,使得即使安装具有低强度的半导体元件也不会发生裂纹。 半导体器件的封装形成为包括多个导电层和绝缘树脂层的多层的叠层,所述多个导电层和绝缘树脂层彼此交替层叠,并且在层叠体的一个表面上具有用于安装半导体元件的部分。 至少包括用于安装半导体元件的部分和其周边的层压体的绝缘树脂层的整个区域或某些区域由通过浸渍液晶聚合物的织物而获得的预浸料 绝缘树脂。
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公开(公告)号:US20100155933A1
公开(公告)日:2010-06-24
申请号:US12659081
申请日:2010-02-24
IPC分类号: H01L23/48
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
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公开(公告)号:US20050006744A1
公开(公告)日:2005-01-13
申请号:US10855979
申请日:2004-05-28
IPC分类号: H01L23/12 , H01L21/44 , H01L23/14 , H01L23/32 , H01L23/498 , H05K1/00 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/46
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止在半导体元件和安装半导体元件的半导体封装之间的接合部分中产生应力,使得即使安装具有小强度的半导体元件也不会发生裂纹。 半导体器件用封装形成为具有交替层叠的多个导电层和绝缘树脂层的多层的叠层体(20),在叠层体的一个面上具有用于安装半导体元件的部分 。 层叠体的绝缘树脂层(20d〜20f)的整个区域或部分区域至少包括半导体元件的安装部分及其周边部分,由浸渍有液晶的机织织物 聚合物与绝缘树脂。
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公开(公告)号:US07696617B2
公开(公告)日:2010-04-13
申请号:US11892927
申请日:2007-08-28
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
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公开(公告)号:US07285856B2
公开(公告)日:2007-10-23
申请号:US10855979
申请日:2004-05-28
IPC分类号: H05K3/46
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止在半导体元件和安装半导体元件的半导体封装之间的接合部分中产生应力,使得即使安装具有小强度的半导体元件也不会发生裂纹。 半导体器件用封装形成为具有交替层叠的多个导电层和绝缘树脂层的多层的叠层体(20),在叠层体的一个面上具有用于安装半导体元件的部分 。 至少包括用于安装半导体元件的部分及其周边的层压体的绝缘树脂层(20d至20f)的整个区域或一些区域由通过浸渍 具有绝缘树脂的液晶聚合物。
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