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公开(公告)号:US20080042258A1
公开(公告)日:2008-02-21
申请号:US11892927
申请日:2007-08-28
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止或减轻用于安装半导体元件的半导体元件和半导体封装之间的接合部分中的应力的发生,使得即使安装具有低强度的半导体元件也不会发生裂纹。 半导体器件的封装形成为包括多个导电层和绝缘树脂层的多层的叠层,所述多个导电层和绝缘树脂层彼此交替层叠,并且在层叠体的一个表面上具有用于安装半导体元件的部分。 至少包括用于安装半导体元件的部分和其周边的层压体的绝缘树脂层的整个区域或某些区域由通过浸渍液晶聚合物的织物而获得的预浸料 绝缘树脂。
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公开(公告)号:US20100155114A1
公开(公告)日:2010-06-24
申请号:US12659080
申请日:2010-02-24
IPC分类号: H05K1/03
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止或减轻用于安装半导体元件的半导体元件和半导体封装之间的接合部分中的应力的发生,使得即使安装具有低强度的半导体元件也不会发生裂纹。 半导体器件的封装形成为包括多个导电层和绝缘树脂层的多层的叠层,所述多个导电层和绝缘树脂层彼此交替层叠,并且在层叠体的一个表面上具有用于安装半导体元件的部分。 至少包括用于安装半导体元件的部分和其周边的层压体的绝缘树脂层的整个区域或某些区域由通过浸渍液晶聚合物的织物而获得的预浸料 绝缘树脂。
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公开(公告)号:US20100155933A1
公开(公告)日:2010-06-24
申请号:US12659081
申请日:2010-02-24
IPC分类号: H01L23/48
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
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公开(公告)号:US20050006744A1
公开(公告)日:2005-01-13
申请号:US10855979
申请日:2004-05-28
IPC分类号: H01L23/12 , H01L21/44 , H01L23/14 , H01L23/32 , H01L23/498 , H05K1/00 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/46
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止在半导体元件和安装半导体元件的半导体封装之间的接合部分中产生应力,使得即使安装具有小强度的半导体元件也不会发生裂纹。 半导体器件用封装形成为具有交替层叠的多个导电层和绝缘树脂层的多层的叠层体(20),在叠层体的一个面上具有用于安装半导体元件的部分 。 层叠体的绝缘树脂层(20d〜20f)的整个区域或部分区域至少包括半导体元件的安装部分及其周边部分,由浸渍有液晶的机织织物 聚合物与绝缘树脂。
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公开(公告)号:US07696617B2
公开(公告)日:2010-04-13
申请号:US11892927
申请日:2007-08-28
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
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公开(公告)号:US07285856B2
公开(公告)日:2007-10-23
申请号:US10855979
申请日:2004-05-28
IPC分类号: H05K3/46
CPC分类号: H05K3/4688 , H01L23/145 , H01L23/49822 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H05K1/0271 , H05K1/0366 , H05K2201/0133 , H05K2201/0141 , H05K2201/0278 , H05K2201/029 , H05K2201/068 , H05K2201/09036 , H05K2201/10674
摘要: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.
摘要翻译: 为了防止在半导体元件和安装半导体元件的半导体封装之间的接合部分中产生应力,使得即使安装具有小强度的半导体元件也不会发生裂纹。 半导体器件用封装形成为具有交替层叠的多个导电层和绝缘树脂层的多层的叠层体(20),在叠层体的一个面上具有用于安装半导体元件的部分 。 至少包括用于安装半导体元件的部分及其周边的层压体的绝缘树脂层(20d至20f)的整个区域或一些区域由通过浸渍 具有绝缘树脂的液晶聚合物。
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公开(公告)号:US07164198B2
公开(公告)日:2007-01-16
申请号:US10649745
申请日:2003-08-28
申请人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
发明人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
CPC分类号: H05K3/0061 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H05K1/0271 , H05K3/205 , H05K3/3457 , H05K3/4644 , H05K2201/09472 , H05K2201/0969 , H05K2201/2009 , H05K2203/1536
摘要: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.
摘要翻译: 一种用于半导体器件的多层衬底,其具有由多组导体层和绝缘层形成的多层衬底本体,并且具有用于安装半导体元件的面和用于外部连接端子的另一面,用于安装的面 半导体器件设置有衬底,衬底通过该焊盘连接到要安装在其上的半导体元件,并且用于外部连接端子的面设置有衬底,衬底通过该衬垫连接到外部电路,其中加强板是 分别连接到用于在其上安装半导体元件的面和多层基板主体的外部连接端子的表面。
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公开(公告)号:US06759739B2
公开(公告)日:2004-07-06
申请号:US10281163
申请日:2002-10-28
申请人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
发明人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
IPC分类号: H01L2312
CPC分类号: H05K3/0061 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H05K1/0271 , H05K3/205 , H05K3/3457 , H05K3/4644 , H05K2201/09472 , H05K2201/0969 , H05K2201/2009 , H05K2203/1536
摘要: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.
摘要翻译: 一种用于半导体器件的多层衬底,其具有由多组导体层和绝缘层形成的多层衬底本体,并且具有用于安装半导体元件的面和用于外部连接端子的另一面,用于安装的面 半导体器件设置有衬底,衬底通过该焊盘连接到要安装在其上的半导体元件,并且用于外部连接端子的面设置有衬底,衬底通过该衬垫连接到外部电路,其中加强板是 分别连接到用于在其上安装半导体元件的面和多层基板主体的外部连接端子的表面。
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公开(公告)号:US07196426B2
公开(公告)日:2007-03-27
申请号:US10995384
申请日:2004-11-24
申请人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
发明人: Jyunichi Nakamura , Tadashi Kodaira , Shunichiro Matsumoto , Hironari Aratani , Takanori Tabuchi , Takeshi Chino
IPC分类号: H01L23/48 , H01L23/498 , H05K3/00 , H05K3/34 , H05K1/02
CPC分类号: H05K3/0061 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H05K1/0271 , H05K3/205 , H05K3/3457 , H05K3/4644 , H05K2201/09472 , H05K2201/0969 , H05K2201/2009 , H05K2203/1536
摘要: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.
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公开(公告)号:US06988312B2
公开(公告)日:2006-01-24
申请号:US10451850
申请日:2002-10-29
申请人: Jyunichi Nakamura , Shunichiro Matsumoto , Tadashi Kodaira , Hironari Aratani , Takanori Tabuchi , Takeshi Chino , Kiyotaka Shimada
发明人: Jyunichi Nakamura , Shunichiro Matsumoto , Tadashi Kodaira , Hironari Aratani , Takanori Tabuchi , Takeshi Chino , Kiyotaka Shimada
IPC分类号: H05K3/26
CPC分类号: H05K3/4682 , H01L21/4857 , H01L23/3128 , H01L23/36 , H01L23/4334 , H01L2224/16 , H01L2924/00014 , H01L2924/01078 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H05K3/0097 , H05K3/205 , H05K3/3473 , H05K3/4007 , H05K3/4644 , H05K2201/0367 , H05K2203/0152 , H05K2203/0376 , H05K2203/1536 , Y10T29/49126 , Y10T29/49128 , Y10T29/49142 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2224/0401
摘要: The invention relates a method for producing a multilayer circuit board (50) for a semiconductor device, comprising using a composite metal sheet (14) in which two metal sheets are combined, forming, on each side of the composite metal sheet, pads for connecting to a semiconductor element, the pads being made of a metal material which is substantially not etched by an etchant for the metal sheet, and an insulating layer having openings exposing the pads, forming, on the insulating layer, a wiring line layer (26) connected to the pads and having pads for connecting to another wiring line layer to be subsequently formed, subsequently fabricating a multilayer circuit board body (20) by necessary numbers of insulating layers and wiring line layers alternately formed, forming, on the outermost insulating layer of the multilayer circuit board body, an insulating layer provided with through-holes exposing pads for external connecting terminals, which are located on the outermost insulating layer, then dividing the composite metal sheet, to yield intermediates (34) each provided on one side of the metal sheet with the multilayer circuit board body, and etching the metal sheet at an area at which a semiconductor element is to be mounted to remove the material of the metal sheet at that area, to thereby form a frame (10) surrounding the area for the mounting of the semiconductor element.
摘要翻译: 本发明涉及一种用于半导体器件的多层电路板(50)的制造方法,其特征在于,使用复合金属片(14),其中组合有两个金属片,在复合金属片的每一侧上形成用于连接的焊盘 对于半导体元件,所述焊盘由金属材料制成,所述金属材料基本上不被所述金属板的蚀刻剂蚀刻,以及具有暴露所述焊盘的开口的绝缘层,在所述绝缘层上形成布线层(26) 连接到焊盘并具有用于连接到随后形成的另一布线层的焊盘,随后通过必要数量的交替形成的绝缘层和布线层来制造多层电路板主体(20),在绝缘层的最外层 多层电路板主体,设置有位于最外侧绝缘体上的用于外部连接端子的通孔露出焊盘的绝缘层 然后分割复合金属板,得到各自设置在金属板的一侧上的多层电路板体的中间体(34),并在要安装半导体元件的区域上蚀刻金属片 在该区域移除金属片的材料,从而形成围绕用于安装半导体元件的区域的框架(10)。
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