公开(公告)号：US08558396B2

公开(公告)日：2013-10-15

申请号：US13325764

申请日：2011-12-14

申请人： Nikhil Vishwanath Kelkar ,  Sagar Pushpala ,  Seshasayee sS. Ankireddi

发明人： Nikhil Vishwanath Kelkar ,  Sagar Pushpala ,  Seshasayee sS. Ankireddi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/061 ,  H01L2224/0615 ,  H01L2224/06155 ,  H01L2224/1134 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

摘要翻译： 提供了半导体器件，并且包括半导体管芯，以及多个接合焊盘，其具有在半导体管芯上以交替交错图案排列的暴露表面。 接合焊盘的每个表面具有与第二焊接放置区域重叠的第一焊接放置区域，其中第一焊接放置区域具有与第二焊接放置区域的长轴正交的长轴。 连接接合位于一个或多个接合焊盘上的第一接合位置区域和第二接合位置区域的长轴的交点处。

公开(公告)号：US20130181332A1

公开(公告)日：2013-07-18

申请号：US13611754

申请日：2012-09-12

申请人： Nikhil Vishwanath Kelkar ,  Kai Liu

发明人： Nikhil Vishwanath Kelkar ,  Kai Liu

IPC分类号： H01L23/495 ,  H01R43/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48141 ,  H01L2224/48145 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

摘要翻译： 用于器件封装的引线框的实施例不仅用于对外部世界的I / O引脚的结构支持和连接，还用于引导框架上方和下方的外壳和/或安装设备。 导电框架还用作一个器件上的焊盘之间的低电阻互连和良好的电流载体，或者位于引线框架上方和/或下方的不同器件上的焊盘之间。

公开(公告)号：US08445998B1

公开(公告)日：2013-05-21

申请号：US12712170

申请日：2010-02-24

申请人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

发明人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

摘要翻译： 半导体封装包括引线结构，其上安装半导体管芯，其中至少一些引线的至少一部分延伸到封装的轴线或轴线处，或跨越封装的轴线或轴线，以阻止封装的热诱导生长， 减小或最小化包装内的应变和与之相关的可靠性问题。

公开(公告)号：US07714415B2

公开(公告)日：2010-05-11

申请号：US11453216

申请日：2006-06-15

申请人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

发明人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

摘要翻译： 半导体封装包括引线结构，其上安装半导体管芯，其中至少一些引线的至少一部分延伸到封装的轴线或轴线处，或跨越封装的轴线或轴线，以阻止封装的热诱导生长， 减小或最小化包装内的应变和与之相关联的可靠性。

公开(公告)号：US07642175B1

公开(公告)日：2010-01-05

申请号：US11542817

申请日：2006-10-03

申请人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

发明人： Viraj A. Patwardhan ,  Lian Hee Tan ,  Nikhil Vishwanath Kelkar

IPC分类号： H01L21/46

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/552 ,  H01L24/27 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2223/5448 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.

摘要翻译： 描述了在集成电路器件的背面上形成保护涂层的晶片级方法。 一方面，将具有背涂层和安装层的带施加到晶片的背面。 背涂层被固化或设置成使得背涂层固定到晶片的背面。 此后，除去背涂层/安装带的安装层，同时留下附着在集成电路器件背面的背涂层。 在一些实施例中，安装层包括当暴露于UV光时释放的紫外线（UV）敏感的粘合剂材料。 所描述的布置可以用于形成具有非常薄的保护性底涂层的集成电路。 作为示例，可以容易地获得厚度在5至50微米范围内的不透明保护膜。

公开(公告)号：US06972244B1

公开(公告)日：2005-12-06

申请号：US10831390

申请日：2004-04-23

申请人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar ,  You Chye How ,  Tian Oon Goh ,  Soi Chong Low

发明人： Viraj A. Patwardhan ,  Nikhil Vishwanath Kelkar ,  You Chye How ,  Tian Oon Goh ,  Soi Chong Low

IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/68 ,  H01L21/78 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.

摘要翻译： 描述了用于标记集成电路器件的背面的晶片级技术。 在由安装带支撑的同时激光标记晶片的背面。 在一些实施例中，安装带足够透明，使得激光穿过安装带并标记晶片的背面。 在其它实施例中，在标记过程中，激光器实际上可燃烧安装带（或其部分）。 标记可以在包括聚合物背涂层，金属化膜或直接在半导体材料上的任何合适的背面材料上进行。

公开(公告)号：US06448632B1

公开(公告)日：2002-09-10

申请号：US09649264

申请日：2000-08-28

申请人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar ,  Ken Pham

发明人： Hem P. Takiar ,  Nikhil Vishwanath Kelkar ,  Ken Pham

IPC分类号： H01L23552

CPC分类号： H01L23/544 ,  H01L23/552 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device comprising a mark located on a surface of the semiconductor device and a metal layer covering the marked surface and the mark. The metal layer functions to protect the semiconductor device from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes. The present invention also pertains a method of manufacturing the semiconductor device as described. The method involves forming a mark on a semiconductor substrate surface of the device and covering the semiconductor substrate surface and the mark with a layer of metal so that the device is protected from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes.

摘要翻译： 一种半导体器件，包括位于半导体器件的表面上的标记和覆盖标记表面的金属层和标记。 金属层用于保护半导体器件免受电磁辐射的影响，并允许标记为了识别而可见。 本发明还涉及制造如上所述的半导体器件的方法。 该方法包括在器件的半导体衬底表面上形成标记，并用金属层覆盖半导体衬底表面和标记，使得器件免受暴露于电磁辐射的影响，并允许标记为识别目的而可见。

公开(公告)号：US09723766B2

公开(公告)日：2017-08-01

申请号：US13035792

申请日：2011-02-25

申请人： Jian Yin ,  Nikhil Vishwanath Kelkar ,  Michael Althar

发明人： Jian Yin ,  Nikhil Vishwanath Kelkar ,  Michael Althar

IPC分类号： H01L23/552 ,  H05K9/00

CPC分类号： H05K9/0007 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/48091 ,  Y10T29/49002 ,  H01L2924/00014

摘要： An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components.

公开(公告)号：US09607917B2

公开(公告)日：2017-03-28

申请号：US12962053

申请日：2010-12-07

申请人： Zaki Moussaoui ,  Nikhil Vishwanath Kelkar

发明人： Zaki Moussaoui ,  Nikhil Vishwanath Kelkar

IPC分类号： H01R9/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/64 ,  H01L25/16 ,  H01L25/00

CPC分类号： H01L23/645 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49575 ,  H01L24/96 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H05K3/3447 ,  H05K3/3484 ,  H05K3/3494 ,  Y10T29/4902 ,  H01L2924/00

摘要： An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.

公开(公告)号：US20130015592A1

公开(公告)日：2013-01-17

申请号：US13325764

申请日：2011-12-14

申请人： Nikhil Vishwanath Kelkar ,  Sagar Pushpala ,  Seshasayee sS. Ankireddi

发明人： Nikhil Vishwanath Kelkar ,  Sagar Pushpala ,  Seshasayee sS. Ankireddi

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L21/283

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/061 ,  H01L2224/0615 ,  H01L2224/06155 ,  H01L2224/1134 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

摘要翻译： 提供了半导体器件，并且包括半导体管芯，以及多个接合焊盘，其具有在半导体管芯上以交替交错图案排列的暴露表面。 接合焊盘的每个表面具有与第二焊接放置区域重叠的第一焊接放置区域，其中第一焊接放置区域具有与第二焊接放置区域的长轴正交的长轴。 连接接合位于一个或多个接合焊盘上的第一接合位置区域和第二接合位置区域的长轴的交点处。