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1.发明授权Integrated circuit device package having a support coating for improved reliability during temperature cycling 有权具有用于在温度循环期间提高可靠性的支撑涂层的集成电路器件封装公开(公告)号：US07423337B1
公开(公告)日：2008-09-09
申请号：US10707208
申请日：2003-11-26
IPC分类号： H01L23/02
CPC分类号： H01L21/563 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/81 , H01L29/0657 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/16058 , H01L2224/16225 , H01L2224/274 , H01L2224/73203 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/01031 , H01L2924/3512 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An apparatus and method for increasing integrated circuit device package reliability is disclosed. According to one embodiment of the present invention, a support coating is added to a wafer after solder bumps have been added but prior to dicing. This support coating or underfill layer provides added strength to the eventual reflowed solder connections, such that the operational lifetime of these connections is increased with respect to failure due to temperature cycling.
摘要翻译： 公开了一种提高集成电路器件封装可靠性的装置和方法。 根据本发明的一个实施例，在添加了焊料凸块之后但是在切割之前，将支撑涂层添加到晶片。 该支撑涂层或底部填充层为最终的回流焊接连接提供了附加的强度，使得这些连接的操作寿命相对于温度循环引起的故障而增加。
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2.发明授权Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages 有权用于形成用于半导体晶片级芯片级封装的预先施加的底部填充粘合剂层的装置公开(公告)号：US07301222B1
公开(公告)日：2007-11-27
申请号：US10366067
申请日：2003-02-12
IPC分类号： H01L23/544
CPC分类号： H01L23/3185 , H01L21/561 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/11849 , H01L2224/16225 , H01L2224/16227 , H01L2224/26145 , H01L2224/2732 , H01L2224/27416 , H01L2224/27515 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/743 , H01L2224/81191 , H01L2224/81815 , H01L2224/83051 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/83951 , H01L2224/9211 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/10156 , H01L2924/10157 , H01L2924/14 , H01L2224/11 , H01L2224/27 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/05099 , H01L2924/00 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.
摘要翻译： 一种用于在安装到基板上时增强组装的晶片级芯片级封装周围的圆角形成的装置和方法。 该方法包括在半导体晶片的第一表面上制造多个集成电路管芯，每个集成电路管芯由晶片上的划线分开。 一旦电路被制造，沿着半导体晶片的第一表面上的划线形成凹槽。 然后，半导体晶片的第一表面被一层底层填充材料覆盖，包括在沿着半导体晶片的第一表面上的划线形成的凹槽内。 在晶片被切割之后，所得模具包括第一顶表面和第二底表面以及四个侧表面。 集成电路形成在模具的第一表面上。 通过切割凹槽产生的凹陷区域形成在模具的所有四个侧表面上并填充有底部填充材料。 当模具安装到基板上时，凹槽区域中的额外的底部填充材料有助于形成比其他可能的更坚固的圆角。
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公开(公告)号：US07015064B1
公开(公告)日：2006-03-21
申请号：US10830818
申请日：2004-04-23
CPC分类号： H01L21/6835 , H01L21/67282 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L24/27 , H01L2221/68327 , H01L2221/6834 , H01L2223/54473 , H01L2223/5448 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/274 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Wafer level techniques for marking the back surfaces of integrated circuit devices are described. A wafer mounting tape is provided that includes releasable pigments. The pigments can be released by exposing the mounting tape to a selected frequency of electromagnetic radiation (e.g., UV light). The released pigments mark the back surface of the wafer. The exposure and pigmentation may be controlled using a variety of techniques including servo control of a light source, the use of masks or reticles or other suitable techniques. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
摘要翻译： 描述了用于标记集成电路器件的背面的晶片级技术。 提供了包括可释放颜料的晶片安装带。 可以通过将安装带暴露于选定频率的电磁辐射（例如，UV光）来释放颜料。 释放的颜料标记晶片的背面。 可以使用包括光源的伺服控制，掩模或掩模版的使用或其它合适技术的各种技术来控制曝光和色素沉着。 标记可以在包括聚合物背涂层，金属化膜或直接在半导体材料上的任何合适的背面材料上进行。
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公开(公告)号：US07135385B1
公开(公告)日：2006-11-14
申请号：US10830820
申请日：2004-04-23
IPC分类号： H01L21/46
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/552 , H01L24/27 , H01L24/81 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2223/5448 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/274 , H01L2224/81801 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.
摘要翻译： 描述了在集成电路器件的背面上形成保护涂层的晶片级方法。 一方面，将具有背涂层和安装层的带施加到晶片的背面。 背涂层被固化或设置成使得背涂层固定到晶片的背面。 此后，除去背涂层/安装带的安装层，同时留下附着在集成电路器件背面的背涂层。 在一些实施例中，安装层包括当暴露于UV光时释放的紫外线（UV）敏感的粘合剂材料。 所描述的布置可以用于形成具有非常薄的保护性底涂层的集成电路。 作为示例，可以容易地获得厚度在5至50微米范围内的不透明保护膜。
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5.发明授权Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages 有权用于形成用于半导体晶片级芯片级封装的预先施加的底部填充粘合剂层的装置公开(公告)号：US07413927B1
公开(公告)日：2008-08-19
申请号：US11264604
申请日：2005-10-31
CPC分类号： H01L23/3185 , H01L21/561 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/11849 , H01L2224/16225 , H01L2224/16227 , H01L2224/26145 , H01L2224/2732 , H01L2224/27416 , H01L2224/27515 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/743 , H01L2224/81191 , H01L2224/81815 , H01L2224/83051 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/83951 , H01L2224/9211 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/10156 , H01L2924/10157 , H01L2924/14 , H01L2224/11 , H01L2224/27 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/05099 , H01L2924/00 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.
摘要翻译： 一种用于在安装到基板上时增强组装的晶片级芯片级封装周围的圆角形成的装置和方法。 该方法包括在半导体晶片的第一表面上制造多个集成电路管芯，每个集成电路管芯由晶片上的划线分开。 一旦电路被制造，沿着半导体晶片的第一表面上的划线形成凹槽。 然后，半导体晶片的第一表面被一层底层填充材料覆盖，包括在沿着半导体晶片的第一表面上的划线形成的凹槽内。 在晶片被切割之后，所得模具包括第一顶表面和第二底表面以及四个侧表面。 集成电路形成在模具的第一表面上。 通过切割凹槽产生的凹陷区域形成在模具的所有四个侧表面上并填充有底部填充材料。 当模具安装到基板上时，凹槽区域中的额外的底部填充材料有助于形成比其他可能的更坚固的圆角。
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公开(公告)号：US20110024910A1
公开(公告)日：2011-02-03
申请号：US12904988
申请日：2010-10-14
IPC分类号： H01L23/492 , H01L21/768
CPC分类号： H01L24/03 , H01L22/32 , H01L24/05 , H01L24/13 , H01L2224/03462 , H01L2224/0391 , H01L2224/0401 , H01L2224/05007 , H01L2224/05016 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/131 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks.
摘要翻译： 描述了改进的保护性金属化布置，其在凸起的铜顶型半导体芯片中特别有用。 在本发明的一个方面，半导体器件包括集成电路并具有顶部晶片制造钝化层。 多个I / O焊盘通过形成在顶部晶片制造钝化层中的接触焊盘开口露出。 在顶部晶片制造钝化层上形成图案化的铜层。 图案化的铜层通过接触焊盘开口电耦合到接触焊盘。 金属阻挡层设置在接触焊盘和图案化铜层之间。 钛金属化层覆盖图案化的铜层的至少部分，并且优选与阻挡层配合以包围接触焊盘区域中的铜层。 第一铝金属化层覆盖钛金属化层的至少一部分。 电绝缘保护层覆盖在第一铝金属化层和顶部晶片制造钝化层之间。 保护层优选由有机材料形成并且包括多个接触开口。 底部金属化叠层形成在接触开口中。 每个底部浸渍金属化叠层通过其保护层中的相关接触开口与第一铝金属化层电连接。 然后优选将焊料凸块粘附到下凸点金属化叠层。
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公开(公告)号：US07642175B1
公开(公告)日：2010-01-05
申请号：US11542817
申请日：2006-10-03
IPC分类号： H01L21/46
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/552 , H01L24/27 , H01L24/81 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2223/5448 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/274 , H01L2224/81801 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.
摘要翻译： 描述了在集成电路器件的背面上形成保护涂层的晶片级方法。 一方面，将具有背涂层和安装层的带施加到晶片的背面。 背涂层被固化或设置成使得背涂层固定到晶片的背面。 此后，除去背涂层/安装带的安装层，同时留下附着在集成电路器件背面的背涂层。 在一些实施例中，安装层包括当暴露于UV光时释放的紫外线（UV）敏感的粘合剂材料。 所描述的布置可以用于形成具有非常薄的保护性底涂层的集成电路。 作为示例，可以容易地获得厚度在5至50微米范围内的不透明保护膜。
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公开(公告)号：US07253078B1
公开(公告)日：2007-08-07
申请号：US10224291
申请日：2002-08-19
IPC分类号： H01L21/44
CPC分类号： H01L24/29 , H01L21/563 , H01L24/11 , H01L24/27 , H01L24/73 , H01L24/92 , H01L29/0657 , H01L2224/0401 , H01L2224/05557 , H01L2224/05568 , H01L2224/1131 , H01L2224/1141 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/13007 , H01L2224/13023 , H01L2224/131 , H01L2224/16238 , H01L2224/2732 , H01L2224/274 , H01L2224/2747 , H01L2224/27515 , H01L2224/27849 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29388 , H01L2224/73104 , H01L2224/73204 , H01L2224/81815 , H01L2224/83191 , H01L2224/83856 , H01L2224/9211 , H01L2224/94 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/10155 , H01L2924/10157 , H01L2924/10329 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/01031 , H01L2924/3512 , H01L2224/05552 , H01L2224/27 , H01L2224/11
摘要： An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.
摘要翻译： 描述了一种在晶片形式的集成电路上形成底层填料层的装置和方法。 在一个实施例中，底层填充粘合剂层被设置并部分地固化在晶片的活性表面上。 一旦底部填充粘合剂已部分固化，则晶片被切割。 然后将各个集成电路或管芯安装到诸如印刷电路板的基板上。 当集成电路的焊球回流以形成与基板上的相应接触焊盘的接头时，底部填充粘合剂回流并完全固化。 在替代实施例中，底部填充粘合剂在其被设置在晶片的有效表面之后被完全固化。
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公开(公告)号：US07095116B1
公开(公告)日：2006-08-22
申请号：US10726042
申请日：2003-12-01
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05082 , H01L2224/05558 , H01L2224/05624 , H01L2224/13023 , H01L2224/131 , H01L2924/00013 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： An apparatus and method for providing aluminum free under bump metallization stacks in an integrated circuit device is disclosed. Included is the use of vias having substantially non-vertical sidewalls that are formed in a resilient layer, such as benzocyclobutene. In general, semiconductor wafers having a plurality of dice are created, with each die having a plurality of contact pads that are formed on the active surface of the wafer. One or more passivation layers are formed on the active surface and etched appropriately to form vias coupled to the contact pads. At least one resilient layer is then disposed atop the top passivation layer and etched appropriately to form vias aligned with and smaller than the passivation layer vias, such that at least part of the contact pads but no part of the passivation layer is exposed. A plurality of UBM stacks are then formed atop the exposed contact pads and resilient layer, with each UBM stack having a plurality of layers, none of which are aluminum layers. Solder bumps are then formed atop each UBM stack.
摘要翻译： 公开了一种用于在集成电路装置中提供无铝凸块金属化叠层的装置和方法。 包括使用具有形成在弹性层中的基本上非垂直侧壁的通孔，例如苯并环丁烯。 通常，产生具有多个骰子的半导体晶片，每个管芯具有形成在晶片的有效表面上的多个接触焊盘。 一个或多个钝化层形成在有源表面上并被适当地蚀刻以形成耦合到接触焊盘的通孔。 然后将至少一个弹性层设置在顶部钝化层顶部并适当地蚀刻以形成与钝化层通孔对准并且小于钝化层通孔的通孔，使得暴露出至少部分接触焊盘但不包括钝化层的一部分。 然后，多个UBM堆叠形成在暴露的接触焊盘和弹性层的顶部，每个UBM堆叠具有多个层，其中没有一个是铝层。 然后在每个UBM堆叠顶部形成焊料凸块。
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公开(公告)号：US06972244B1
公开(公告)日：2005-12-06
申请号：US10831390
申请日：2004-04-23
IPC分类号： H01L21/301 , H01L21/46 , H01L21/68 , H01L21/78 , H01L23/544
CPC分类号： H01L21/78 , H01L21/6835 , H01L21/6836 , H01L23/544 , H01L24/27 , H01L2221/68327 , H01L2221/6834 , H01L2223/54473 , H01L2223/5448 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/274 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
摘要翻译： 描述了用于标记集成电路器件的背面的晶片级技术。 在由安装带支撑的同时激光标记晶片的背面。 在一些实施例中，安装带足够透明，使得激光穿过安装带并标记晶片的背面。 在其它实施例中，在标记过程中，激光器实际上可燃烧安装带（或其部分）。 标记可以在包括聚合物背涂层，金属化膜或直接在半导体材料上的任何合适的背面材料上进行。
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